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Question regarding the SPI TXFIFO in the TM4C

Richard Morawski73
Prodigy 20 points

I am playing around with communications between peripherals using a Tiva Launchpad and I noticed something whilst reading the datasheet for the SPI TXFIFO.

The datasheet says: "In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the transmit FIFO. If less than 8 values have been written to the transmit FIFO since the SSI clock was enabled using the Rn bit in the RCGCSSI register, then 0 is transmitted". This has caused a little bit of confusion for me.

What I don't understand is how can the slave transmit the 8th most recent value in the transmit FIFO if it is empty?

Also does this imply that if the microcontroller is acting as a slave, at least 8 values must be written to the TXFIFO before a valid value can be transferrred on the masters request?  

I am only playing around with peripherals such as OLEDs, LCDs, output port expanders etc so the micro is always master, but I was planning on doing inter-micro communications using SPI later. In this case one of the micros would have to be a slave and my above query would become applicable.

Thank you  

  • 0
    Expert 2415 points

    Think of the FIFO as a ring buffer. When it's "empty", the previous contents haven't actually been erased - it's just that the counters say there's no new data. The SSI must, however, transmit something, so it reuses old data. Upon peripheral reset, the 8-position buffer is initialized as zeroes, hence the "if less than 8 values then 0". That's how it would make sense to me. You could (in)validate this by trying it out!

    Richard Morawski73 said:
    Also does this imply that if the microcontroller is acting as a slave, at least 8 values must be written to the TXFIFO before a valid value can be transferrred on the masters request?

    I don't think so:

    Richard Morawski73 said:
    The datasheet says: "In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the transmit FIFO. ...

    If you've written at least one value to the TX FIFO, then it's not empty and the "special logic" shouldn't apply.

  • 0 in reply to Veikko Immonen
    Prodigy 20 points
    That makes way more sense. It just came down to lack of knowledge of circular buffers. Thank you for the great explanation.