• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 30 subscribers
  • Views 523 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570LS31x/04x Errata CortexR4#66 question

Petr Cvachoucek
Prodigy 10 points
Other Parts Discussed in Thread: HALCOGEN

Hello all,

we have a question related to above mentioned errata. According to the SPNZ195C document, the workaround to this erratum is to set bit [7] of the Auxiliary Control Register to disable out-of order completion for divide instructions. Looking into the startup code generated by HalCoGen, the errata workaround is applied only in the branch executed in case of POWERON_RESET, and not in other reset cases - please could you explain why its not needed e.g. in external reset case (nRST being driven low externally)? It seems to us it should be applied in all cases.

The same question applies for Errata CortexR4#57 workaround.

Thank you

Petr Cvachoucek

  • 0
    TI__Guru 68930 points
    Hi Petr,

    Thanks for reporting this!

    I agree with your assessment - according to the Cortex R4 TRM these bits in the system control coprocessor are reset
    and therefore should be reinitialized after any source of reset of the CPU. SDOCM00115686 is the ticket #.
    In the mean time you should probably add the function calls to _errata_CORTEXR4_66_() and _errata_CORTEXR4_57_() to the other
    reset sequences manually.