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I2C, Handling of 2nd address in slave mode (missing status bits)

Tobi
Intellectual 320 points

Hi,

I am using I2C_5 in slave-mode and want to handle two addresses.

Handling the first address (I2C_SOAR_OAR = 0x56, OnwAddressRegister) by checking

the FBR (FirstByteReceived) and RREQ(ReceiceRequest) bits works perfect. When Master sends I2C data, FBR-Bit and RREQ-Bits are set.

When using the second address (I2C_SOAR2_OAR2 = 0x57, OAR2EN = 1) I can get an Interrupt on the I2C5-Handler, but I am missing

the  FBR (FirstByteReceived) and RREQ(ReceiceRequest) bits (always 0) (I2C_SVR_OAR2SEL-bit is set), means I am not able to handle data transfer for the second address.

Does anyone know why the behavior of FBR and RREQ is different when using second address?

 

Best regards,

Tobi