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What will happen with SSInClk missing a bit?

Other Parts Discussed in Thread: TM4C1294NCPDT

Using SSI/DMA mode continuous transfer

If SSInFss is enabled, such as the ones demonstrated in 17.3.7 of tm4c1294ncpdt.pdf, which error handler will be invoked when SSinClk and SSInFss are not in sync due to communication noise, for example


Not enough SSInClk pulses after SSinFss (a SSInClk pulse is missing)

Too many SSInClk pulses after SSinFss (SSInClk glitches)


Thanks for your reply

  • Hello David,

    There is no error mechanism to find if the pulse is missing or is extra. What is the configuration of SSI being used, master or slave?

    Regards
    Amit
  • Master will have no issue, I am sure its SSI will just use its internal clock to clock in the data, pulses appears on the GPIO do not actually loop back to clock in the data.

    It is the slave I was referring to .

    OK, no error handler will be invoked.

    Then what happens to the data alignment?

    I think the extra SSIClk clock will be simply ignored and possibly a bad data will be fetched depending on the location of the extra pulse, and that's fine for me. If a pulse is missing between SSInFSS, will SSI/DMA fetches a bad data or the bad data is simply discarded, leaving me one data short?

  • Hello David

    SSICLK and FSS are driven lines. Hence if there is noise which causes the CLK to be missing or extra then the effort should be to eliminate the noise source.

    I2C as an example is Open Drain and hence we build the filter to clear out runt pulses.

    Regards
    Amit
  • Thanks, Amit,


    [Added] Unfortunately, in our business, it is not what can be done, but more like what we can compromise based on the budget and target customers

    We deal with industrial environment, for example, a welding machine maybe next to our instrument, in that case, it is still possible to mess up the SSICLK.

    So I would like to get back to the last question: what happens to the data alignment?

    I think the extra SSIClk clock will be simply ignored and possibly a bad data will be fetched depending on the location of the extra pulse, and that's fine for me. If a pulse is missing between SSInFSS, will SSI/DMA fetches a bad data or the bad data is simply discarded, leaving me one data short?

  • Hello David,

    OK. That could still be a problem in industrial space. You are correct. If there is an extra pulse, then the wrong bit may get shifted in provided the runt pulse meets the setup and hold requirement for SSICLK coming to the slave. Similarly the missing clock pulse may cause the data to be incorrect as well.

    Regards
    Amit
  • Will the missing clock pulse drop a data point? e.g. the shifter simply didn't get enough bits before the next FSS, so it simply flush the data to the toilet.
  • Hello David,

    I think we would need to rig up a test where master is configured to send 7 bits and slave is configured for 8 bits, and then send in data patterns to see the Slave response.
    But looking at the logic the early FSS deassertion will load the shift register content as is to the FIFO.

    Regards
    Amit
  • David , are you talking about the external (slave) device or the micro?

    If it is the slave it very much depends on the slave. Simple devices will just output whatever is in their shift register when the select is de-asserted so you will have misaligned data with the wrong number of bits. Some devices will abort if the wrong number of bits are shifted in. Some device will abort on too few bits but not on too many.

    Basically you have to ensure data integrity on the board with shielding, filtering etc...

    Robert
  • If the environment noise can influence the SSI port/lanes, then it can as well influence other hardware, or the microcontroller by itself, so in that case you'll need a complete shielding/filtering of the main board and interface to the external world. Especially, the power supply will need some filtering.

    But if it isn't that bad, you could also add a CRC control byte/word(ok, you'll loose some bandwidth) with each payload, and check for data integrity. Then you could also keep a counter as a test, and check how many packets are received wrong, and take action(hardware shielding) if it gets to high.

  • marc_rir said:
    But if it isn't that bad, you could also add a CRC control byte/word(ok, you'll loose some bandwidth) with each payload, and check for data integrity. Then you could also keep a counter as a test, and check how many packets are received wrong, and take action(hardware shielding) if it gets to high.

    If you are in a position to do that stop fooling around with SPI.  Switch to something like CAN that already supports all of this.

    SPI is designed and meant for simple on-board inter-chip communications in noise-free environments.

    Robert

  • As I said previously, there is no way to fully take care the industrial noise with limited budget, that's why I would like to know the consequence and design around it

    For example, I am expecting a packet of 100 bytes data coming in. when SSClk clock is missing, and TiVa gives me a bad data, that's fine, I will see the DMA Rx finish interrupt and I can look at the checksum at the end to catch the problem. If SSClk missing, and TiVa simply dump the broken data to the toilet, then DMA interrupt will not happen at the end of the transfer, because it had not enough data points (it still waiting for the missing one), then I will have to keep polling the SSI unit to see if I have a time-out

    Of course, a error indicator from SSI will be the easiest solution.

  • Sorry, that wont work(well, you cant just add a CRC value from the slave) , but maybe you could do a test by polling the ID register(if the slave has one) or another known register value, in a loop while making a lot of noise(with the welder) and then check if it really affects the readings.
  • There are a few slaves that generate checksums of some sort on their output IIRC. You are right though that you cannot add one if it doesn't exist. It also would only check one of the possible directions of corruption, although it might allow implicit detection of the other.

    Robert
  • David Chance said:
    As I said previously, there is no way to fully take care the industrial noise with limited budget, that's why I would like to know the consequence and design around it

    Most of the ways of dealing with this are design methods and add little or nothing to the BOM cost. Remember the SPI is only a small subset of the lines to the CPU being corrupted by noise.   There are others that are more important.

    David Chance said:
    For example, I am expecting a packet of 100 bytes data coming in. when SSClk clock is missing, and TiVa gives me a bad data, that's fine, I will see the DMA Rx finish interrupt and I can look at the checksum at the end to catch the problem. If SSClk missing, and TiVa simply dump the broken data to the toilet, then DMA interrupt will not happen at the end of the transfer, because it had not enough data points (it still waiting for the missing one), then I will have to keep polling the SSI unit to see if I have a time-out

    If the micro is the master it won't see a missing clock unless the interference is corrupting the CPU in which case you have larger problems.

    Robert

  • As I mentioned earlier, the micro is a slave
  • Hello David,

    Actually the idea that everyone else may be prompting is to make sure that the SSI lines are shielded well on the board so that occurrence rate is reduced. This will not have an impact on the BOM of the board unless it causes a change in number of layers.

    Regards
    Amit
  • Ahh, that wasn't clear to me.

    You're not running the SPI off board to another board are you?

    Robert
  • Even a change in the number of layers shouldn't add much cost. IMO a board with micros running this fast should have ground and power layers in any case. Changes in routing are free for the BOM.

    Guard rings (recommended in a TI app note BTW) are nearly free, only cost a few vias and coupling to frame..

    RC filters on the lines are cheap, even small ferrite beads on the IO lines are not expensive. Zeners or similar spike protection should be considered. These not only reduce interference but physically protect the device.

    Strong pull-ups are cheap, especially if you use resistors arrays.

    Even small metal cages as faraday cages don't add much, depending on the board size and that's the most expensive option I was thinking of. Thin sheet metal isn't pricey. Not as good as copper perhaps. This would be the last item to consider though.

    Robert
  • David Chance said:
    Yes, off board

    OK, SPI is almost certainly the wrong bus for that use, especially in the environment you are describing.

    Besides the noise problems you are describing you can expect the devices on it to fail electrically.  SPI is designed for single board IC to IC communication.  You can run it through stacked boards especially with properly shielded connections but it lacks the proper drives and protection to run through a cable.

    This is the domain of CAN and RS485.

    Robert

  • Hello Robert.

    I agree. The checksum must be built in and clocking must be eliminated.

    Regards
    Amit
  • I meant off the main board, but still within a stacked system, SPI is suitable for that