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RTIclock hardware interrupts

Dan S17
Expert 1510 points
Other Parts Discussed in Thread: HALCOGEN

I am using a hardware interrupt associated with the compx event of a RTIclock counter.  Does a overflow event on the same counter trigger the same ISR as that associated with the compx event? Kind of looks that way according to the diagram seen in Halcogen in RTI-> RTI General.


Thank you!

  • 0
    Expert 1510 points
    I have another related question. What happens if I enable the interrupts associated the RTIclock and then start the timer but do not set the compx register? Will the compx register have some default value stored in it that will then trigger an RTIclock interrupt?
  • 0
    TI__Intellectual 1855 points

    Hi Dan,

    Overflow and Compare events trigger interrupts on separate VIM channels. They are associated with two different ISRs. The HALCoGen RTI tab shows each interrupt source with separate arrow. Counter1 overflow, Counter2 overflow, Compare1, Compare2, Compare3, Compare4 and Timebase Control are the different interrupt sources in RTI module.

    Thanks and Regards,
    Vineeth

  • 0 in reply to Dan S17
    TI__Intellectual 1855 points
    Hi Dan,

    Yes. The Compare register will be 0 by default. This means you will get an interrupt from this compare block when you start the counter and every time the counter overflows and rolls over to 0.

    I am curious as to why you have the interrupt enabled without loading a compare value. Any specific reason or are you just wondering?

    Thanks and Regards,
    Vineeth
  • 0 in reply to Vineeth Thomas Alex
    Expert 1510 points

    I don't see a way to turn off the interrupt associated with the overflow without turning off the interrupt associated with the compare. Is there a way?

  • 0 in reply to Dan S17
    TI__Intellectual 1855 points

    RTI Set Interrupt Control Register (RTISETINTENA) determines which RTI interrupts are enabled.  You can use the rtiEnableNotification() and rtiDisableNotification() APIs if you are using HALCoGen. You can refer to the TRM for more info (RTI module > Control Registers > RTISETINTENA).

    Thanks and Regards,

    Vineeth