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RTIclock question.

Dan S17
Expert 1510 points
Other Parts Discussed in Thread: HALCOGEN

I have written code that uses hardware interrupts generated when the RTI counter counts up to a value I write to the rtiREG1->CMP[0U].COMPx register. In main() I call rtiStartCounter().

I set the COMPx registers in an ISR associated with a transition on a GIO pin (I will call this my GIO ISR). My problem is that the ISR associated with the COMPx event (I will call this my RTI ISR) is running before I ever receive an interrupt on the GIO pin and this generates an unwanted interrupt. This unwanted RTI ISR runs at about 50 seconds after I load the code to the microcontroller and hit the green go arrow in CCS. I am assuming that this is occurring because once the RTI COMPx interrupt is enabled it will occur at the time that happens to be in the COMPx register (in my case that is 50000000 and I have a prescale factor of 100).  But even if I had a zero in the COMPx it would still generate an interrupt after the time overfllows, right? So I am thinking that to prevent this unwanted interrupt from occurring I could place the call to rtiStartCounter in my GIO ISR. Alternatively within my RTI ISR I could read the value in the COMPx register and only execute the code within the RTI ISR if COMPx is not equal to 50000000 (or some other number).

Is there a better way to stop the effects of this unwanted interrupt?

  • 0
    TI__Intellectual 1855 points

    Hi Dan,

    I think this has been answered in the other thread. 

    Thanks and Regards,
    Vineeth

  • 0 in reply to Vineeth Thomas Alex
    Expert 1510 points

    Hi Vineeth

    I think I need to explain my problem a bit better and I will do so soon. Thanks!

    Dan

  • 0 in reply to Dan S17
    Expert 1510 points

    OK. I think that more clearly I can state my problem as follows.

    I am using the RTI COMPx register to schedule events. The time at which the events should be scheduled are determined at runtime. Having scheduled an event the event will occur at the chosen time. After the event occurs if I don't schedule a new event before the counter overflows and continues to count up to the value presently in COMPx then a unwanted interrupt occurs at that time. So I am wondering how best to address this problem? Should I disable the interrupt associated with COMPx until I need it for the next scheduled event? Or should I stop the counter (with rtStopCounter) as I wait to determine when the next event should be scheduled and then restart the counter (with rtiStartCounter) when that time is known? Or should I find a way to identify these unwanted interrupts and handle the consequence of there occurrence in the associated ISR? Or something else I have not thought of?

  • 0 in reply to Dan S17
    Expert 1510 points

    Additional and related question: Is there a way to zero the counter? It would be great if I could stop the counter and zero it before restarting it. I have looked in the technical reference manual and I don't see mention of zeroing the counter.


    Update: It looks like there is a way to zero the counter given in the manual. It looks like the RTIFRC0 register can be written to reset the counter. There is a note in the manual which states:

    "Note: If counters must be preset, they must be disabled in the RTIGCTRL register to ensure consistency between RTIUC0 and RTIFRC0."

    Does this mean that I need to stop the counter using rtiStopCounter then reset by writing to RTIFRC0 then restart the counter?


    Update 2: Looks like I will also need to reset RTIUC0 as well. Is this correct?

  • 0 in reply to Dan S17
    TI__Intellectual 1855 points

    Yes. Your understanding is correct. There is a rtiResetCounter() API in HALCoGen to zero the counter. You can check that to understand better. You basically have to stop the counter and then clear the UC and FRC registers.

    For your previous question, I think the right way would be to stop the counter and reset it until you need it again(you already figured this out I guess).

    Thanks and Regards,
    Vineeth