Tiva EPI -Fpga interface problem

Hello Krishnan,

What is the system clock frequency you are using? And also please elaborate one cycle-multiple read!!!! Is one cycle you mean one read cycle or one clock cycle?

Regards
Amit

Hello,

Thank you for the message, Our Systemclock is 120 Mhz

g_ui32SysClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |
SYSCTL_OSC_MAIN |
SYSCTL_USE_PLL |
SYSCTL_CFG_VCO_480), 120000000);

Epi Clock 120 Mhz

*****************//
EPIDividerSet(EPI0_BASE, 0);
EPIModeSet(EPI0_BASE, EPI_MODE_GENERAL);
EPIConfigGPModeSet(EPI0_BASE, EPI_GPMODE_DSIZE_16 | EPI_GPMODE_ASIZE_12 |EPI_GPMODE_CLKPIN |EPI_GPMODE_FRAME50 , 10, 0);
EPIAddressMapSet(EPI0_BASE, EPI_ADDR_PER_BASE_C | EPI_ADDR_PER_SIZE_64KB);
EPIFIFOConfig(EPI0_BASE, EPI_FIFO_CONFIG_TX_EMPTY | EPI_FIFO_CONFIG_RX_1_4);

Our configurations are all correct because FPGA DATA we are correctly receiving.

Our issue for every 1024 bytes of data FPGA will raise an interrupt and send data to controller.In interrupt we are receving the data correctly,problem is in every 250us FPGA will raise an interrupt and controller have to send the data out as UDP............

From our experience (individually we checked interrupt,udp.....................)but integrating as a whole controller is going to Fault ISR.So this is the technical issues what  we are facing.

Hope Now doubt is clear to you..............

Please Help

Regards,

Krishnan

 

Sorry, I missed your one question "And also please elaborate one cycle-multiple read!!!! Is one cycle you mean one read cycle or one clock cycle?
"
Actually to read 1024 bytes from FPGA in our configuration ,we are seeing 1024 frames (while we probed).Fpga is dertecting falling Edge of Clock from Controller ,then address,and in next cycle its putting data to controller......This is working fine for now.....But we have to reduce the over all timing to send data out as udp,whic we are receving from FPGA.......


Regards,
Krishnan

Hello Krishnan

Thanks for the clarification. Before optimizing the read transfer (you can see that in the data sheet for General Purpose Mode that FRM50 bit must be cleared) the cause of the Fault ISR must be ascertained. Some details here would help to start the diagnosis.

e2e.ti.com/.../374640

Regards
Amit

Hello Amit,
Frame 50 BIT I CLEARED,but right now my issue is.like in every 250 us(microseconds) FPGA will gave an interrupt with 1024 bytes of data.
Controller have to raed the data and send out it as UDP packet with in 250 us,because in every 250us FPGA interrupt will come........

Individually we checked like
1)Sending out packets as UDP.
2)Receivindg DATA from FPGA.

Both were successfull.

Now problem is coming when we are integrating all modules and seeking help to resolve this issue like first packet will receive and udp is send out but after that code is not able to second packet.......

Any suggestions to resolve this issue..


Please help..

Regards,
Krishnan

Hello Krishnan

You mentioned that there is a Fault that occurs. You would need to debug the cause of the Fault as mentioned in my follow up post

Regards
Amit

OK Amit,

I will do ,just check my previous post ,accordind to your experience  how much time is required for EPI bus to read 1024 bytes in GPMODE WHEM BOTH EPI clock and Sytem Clock is 120mhz...and to send out a packet as UDP in 1024 bytes.......................

Regards,

Krishnan

Hello Krishnan,

Depends on what kind of processing is involved. Do note that code execution while finite may have some level of in deterministic time because of Flash Wait State for CPU execution. Ideally it is not a pipe as you read data from EPI to a SRAM location, then configure the Ethernet for data transmission, wait for the data to be sent (which involves overhead of the LwIP stack).

Regards
Amit

Hello Amit Thank you for the message..

I am attaching my project Folder please try to resolve my issue if possible.

I am receiving data from FPGA every 400 micro seconds and i want to send out it as udp packets...

Intially my working code for udp was as below,it  was working fine,

Hello Krishnan,

It is not possible for me to work on your project for 2 simple reasons: (a) I do not have your setup to replicate and (b) the information on FaultISR analysis is not there either.

Regards
Amit

Hello Krishnan

You cannot put the data from EPI to the EMAC directly. But it is possible to use the destination buffer as the Buffer to be used in the Tx Descriptor of the EMAC.

Regards
Amit