DMA and SPI in compatibility mode transfer is worng

Other Parts Discussed in Thread: RM48L952, HALCOGEN

Hello,

I have 2 RM48L952 and I'm trying to implement an SPI interface between them. The master side is OK, the problem is on the slave. I configured the DMA and I see that it receives data, but the data being read is intermittent.

For test purposes I'm trying to send a simple counter to the slave, 10 bytes but when I do the transfer only even bytes are valid. For example: I should receive 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, but I end up receiving 80 00 81 01 82 02 83 03 84 04 85 05.

Here's my configuration:

DMAConfiguration_t g_slaveConfig_DMA_SPI3_RX =
{
    .ISADDR               = 0xFFF7F840U, // spi + 2 CHECK
    .IDADDR               = (uint32_t)&dma_test_buffer[0],
    .FRAME_COUNT          = 150,
    .ELEMENT_COUNT        = 1,
    .CHCTRL_TRANSFER_TYPE = DMA_TRANSFER_TYPE_FRAME,
    .CHCTRL_AMW           = DMA_AMWR_POSTINCREMENT,
    .CHCTRL_AMR           = DMA_AMWR_CONSTANT,
    .CHCTRL_RES           = DMA_RWES_BYTE,//CHECK DMA_RWES_BYTE,
    .CHCTRL_WES           = DMA_RWES_BYTE,//CHECK DMA_RWES_BYTE,
    .CHCTRL_CHAIN         = CMA_CHAIN_NONE,
    .CHCTRL_AIM           = DMA_AIM_DISABLED,
    .TRIGGER_TYPE         = DMA_TRIGGER_TYPE_HARDWARE_TRIGGER
};

        DMAReg->GCTRL  = 0x00000001U; /* reset dma       */
        DMAReg->GCTRL  = 0x00010000U; /* enable dma      */
        DMAReg->GCTRL |= 0x00000300U; /* stop at suspend */

        /* DMA req assign */
        DMAReg->DREQASI0 = (DMAREQ14 << 24U); /* Map request line 14 to Dma channel 0 */

        /* Setup control packet */
        DMAControl->Packet[DMACH0].ISADDR  = g_slaveConfig_DMA_SPI3_RX.ISADDR;
        DMAControl->Packet[DMACH0].IDADDR  = g_slaveConfig_DMA_SPI3_RX.IDADDR;
        DMAControl->Packet[DMACH0].ITCOUNT = (g_slaveConfig_DMA_SPI3_RX.FRAME_COUNT << 16U)
                                           | (g_slaveConfig_DMA_SPI3_RX.ELEMENT_COUNT);

        DMAControl->Packet[DMACH0].CHCTRL  = ((g_slaveConfig_DMA_SPI3_RX.CHCTRL_CHAIN        << 16U)
                                           | (g_slaveConfig_DMA_SPI3_RX.CHCTRL_RES           << 14U)
                                           | (g_slaveConfig_DMA_SPI3_RX.CHCTRL_WES           << 12U)
                                           | (g_slaveConfig_DMA_SPI3_RX.CHCTRL_TRANSFER_TYPE << 8U)
                                           | (g_slaveConfig_DMA_SPI3_RX.CHCTRL_AMR           << 3U)
                                           | (g_slaveConfig_DMA_SPI3_RX.CHCTRL_AMW           << 1U)
                                           | (g_slaveConfig_DMA_SPI3_RX.CHCTRL_AIM));

        DMAControl->Packet[0].EIOFF  = 0;
        DMAControl->Packet[0].FIOFF  = 0;

        /* Channel 0 port assignment to port B */
        DMAReg->PAR0 |= (4U << 28U);

        /* DMA channel enable */
        DMAReg->HWCHENAS =  (1 << DMACH0);

        /* SPI Dma en (bit 16) */
        SPI3Reg->SPIINT0 |= 0x00010000U;

I also tried using 0xFFF7F843U and 0xFFF7F842U(just in case), following the instructions found in this thread