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code debugging in SRAM

Other Parts Discussed in Thread: HALCOGEN

Hi there,

When I was working on TIVA M4 MCUs, there is a way to directly load the code to SRAM by CCS, and then debug the code in SRAM.

Because the code loading is directly to SRAM, so there is no waste time in flash erase and programming.  However,  in Hercules (RM57), I find my trick in TIVA does not work. (the trick is to modify link command to SRAM only).  It take a lot longer for code loading to flash though only a few sectors were erased. On top of that, there is a concern of flash worn out.

I am wondering is there a procedure to achieve SRAM code loading directly from CCS and debug the code in SRAM?

  • Hello Yuncheng,

    The methodology is usually architecture dependent and there are significant differences between the Hercules and TM4C MCUs. I am forwarding your post to one of our experts on the RM57 so that they may provide advice specific to that part number.
  • Yuncheng Song said:
    However,  in Hercules (RM57), I find my trick in TIVA does not work. (the trick is to modify link command to SRAM only).

    Does your program use HALCoGen?

    This is because the HALCoGen generated start-up code can run a Programmable Built-In Self-Test (PBIST) on the SRAM, which is a destructive test which overwrites the contents of the tested SRAM module.

  • Yuncheng,

    If you want run from RAM, you will need to remove the PBIST test and memory initialization for the SRAM in the start up sequence. To make it easier, I would suggest to disable all self diagnostic and memory initialization in startup code. However, you will need to do a memory initialization for the on-chip SRAM so that all SRAM has valid ECC before loading the code to RAM. You can do it in a gel file. There is more work than expected.

    If you just want to evaluate the performance of a function you can load the function code in Flash and copy it to RAM in runtime.  The following forum thread will provide you with more information.

    Thanks and regards,

    Zahohogn