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EPI Initialization for 1 MByte SRAM - Tiva TM4C1294XL

Other Parts Discussed in Thread: TM4C129XNCZAD

Hi,

I have a 1 MB SRAM interface to the EPI port that I want to initialize properly before I receive my hardware prototype. According to the documentation the following would be sufficient; however, I have seen posts on this board that indicate that the individual port pins must be initialized as well. Is the following code sufficient for the TM4C1294XL Tiva?

Here is my code:

//---------------------------------------------------------------
// EPI Setup
//---------------------------------------------------------------

// Enable the peripheral
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);

// Set the EPI divider. <==== set EPI0_BASE
ROM_EPIDividerSet(EPI0_BASE, 0);

// Select EPI Host Bus 8-bit mode.
ROM_EPIModeSet(EPI0_BASE, EPI_MODE_HB8);

// Configure SRAM mode
// EPIConfigHB8Set - all data transfers use bits[7:0]
ROM_EPIConfigHB8Set(EPI0_BASE, EPI_HB8_MODE_ADDEMUX | EPI_HB8_WRWAIT_0
| EPI_HB8_RDWAIT_0 | EPI_HB8_CSCFG_CS, 0);

// Set the address map. Base 0x6000 0000, Using 1MB out of 16MB addr space
ROM_EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_16MB | EPI_ADDR_RAM_BASE_6);


// Wait for the EPI initialization to complete.
while(HWREG(EPI0_BASE + EPI_O_STAT) & EPI_STAT_INITSEQ)
{

}

// At this point, the SRAM is accessible and available for use.

Thank you,

Joe

  • There is an example reference here for SDRAM.

    http://www.ti.com/tool/TIDM-TM4C129XSDRAM?keyMatch=sdram&tisearch=tidesigns

    The description from the link above.

    "This reference desing demonstrates how to implement and interface SDRAM Memory to the performance microcontroller TM4C129XNCZAD. The implementation is made possible by using the EPI Interface of the Microcontroller to interface a 256Mbit SDRAM at 60MHz which allows developers to implement additional memory for code and data when interfacing with High Speed LCD Panels."

    A reference specifically for SRAM is in the works but not available yet.

    Regards,
    Dave

  • Hi,

    For the individual port configurations I find it surprising that the "ROM_GPIOPinConfigure" is located in ROM whereas the "GPIOPinTypeEPI" is not. For example (D0):

    ROM_GPIOPinConfigure(GPIO_PK0_EPI0S0); // D0
    GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_0);

    So I cannot assume that all of the functions are located in the "Tiva C Series TM4C129x ROM USER'S GUIDE" (spmu363a). That is a subset of the available functions.

    Thanks for your prompt reply,
    Joe
  • Joseph Curasi said:
    ... find it surprising that the "ROM_GPIOPinConfigure" is located in ROM whereas the "GPIOPinTypeEPI" is not

    Might your surprise be bit quelled w/the knowledge that, "GPIOPinConfigure()" has been around (forever) and that, "GPIOPinTypeEPI()" is far newer - thus may not (yet) have been "entombed" w/in ROM?

  • I have the EPI memory configured as per previous example, yet my IAR debugger shows a value of "<error>" for any array placed in extended memory. My EPI initialization is called prior to "__iar_program_start()" and I verified the timing of my OE_, CS_, and WE_ SRAM signals. Any idea why the IAR would flag an error and not write a value?
  • Hello Joseph,

    I am not sure what you mean by <error> value. Could you please elaborate the same?

    Regards
    Amit
  • Hi Amit,

    In my IAR Embedded Workbench IDE is the Watch window. The Watch window contains both an "Expression" and a "Value" field. For any variable or array that is external, the "Value" field is "<Error>".  For internal variables a numerical is shown.

    Joe

  • Hello Joseph,

    OK. So are the access i.e. Read and Write to SRAM working in the main application code?

    Also can you please share the full EPI Configuration code which must include
    1. EPI IO configuration
    2. EPI Module Configuration
    3. Which SRAM you have used and how the h/w schematic looks like for the same?

    Regards
    Amit
  • Hi Amit,
    All the EPI code is below and the SRAM ( ISSI IS61WV10248-TSOP44 ) identifier is indicated.

    // Enable the EPI peripheral
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);

    //---------------------------------------------------------------
    // GPIO PORTS USED FOR EPI
    //---------------------------------------------------------------

    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOP);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);



    // Data Bus (D7:D0)
    ROM_GPIOPinConfigure(GPIO_PK0_EPI0S0); // D0
    GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_0);

    ROM_GPIOPinConfigure(GPIO_PK1_EPI0S1);
    GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_1);

    ROM_GPIOPinConfigure(GPIO_PK2_EPI0S2);
    GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_2);

    ROM_GPIOPinConfigure(GPIO_PK3_EPI0S3);
    GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_3);

    ROM_GPIOPinConfigure(GPIO_PC7_EPI0S4);
    GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_7);

    ROM_GPIOPinConfigure(GPIO_PC6_EPI0S5);
    GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_6);

    ROM_GPIOPinConfigure(GPIO_PC5_EPI0S6);
    GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_5);

    ROM_GPIOPinConfigure(GPIO_PC4_EPI0S7); // D7
    GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_4);

    // Control Signals
    ROM_GPIOPinConfigure(GPIO_PP3_EPI0S30); // CE_
    GPIOPinTypeEPI(GPIO_PORTP_BASE, GPIO_PIN_3);

    ROM_GPIOPinConfigure(GPIO_PP2_EPI0S29); // WE_
    GPIOPinTypeEPI(GPIO_PORTP_BASE, GPIO_PIN_2);

    ROM_GPIOPinConfigure(GPIO_PB3_EPI0S28); // OE_
    GPIOPinTypeEPI(GPIO_PORTB_BASE, GPIO_PIN_3);

    // Address Bus (A19:A0)
    ROM_GPIOPinConfigure(GPIO_PA6_EPI0S8); // A0
    GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_6);

    ROM_GPIOPinConfigure(GPIO_PA7_EPI0S9);
    GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_7);

    ROM_GPIOPinConfigure(GPIO_PG1_EPI0S10);
    GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_1);

    ROM_GPIOPinConfigure(GPIO_PG0_EPI0S11);
    GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_0);

    ROM_GPIOPinConfigure(GPIO_PM3_EPI0S12);
    GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_3);

    ROM_GPIOPinConfigure(GPIO_PM2_EPI0S13);
    GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_2);

    ROM_GPIOPinConfigure(GPIO_PM1_EPI0S14);
    GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_1);

    ROM_GPIOPinConfigure(GPIO_PM0_EPI0S15);
    GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_0);

    ROM_GPIOPinConfigure(GPIO_PL0_EPI0S16);
    GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_0);

    ROM_GPIOPinConfigure(GPIO_PL1_EPI0S17);
    GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_1);

    ROM_GPIOPinConfigure(GPIO_PL2_EPI0S18);
    GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_2);

    ROM_GPIOPinConfigure(GPIO_PL3_EPI0S19);
    GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_3);

    ROM_GPIOPinConfigure(GPIO_PQ0_EPI0S20);
    GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_0);

    ROM_GPIOPinConfigure(GPIO_PQ1_EPI0S21);
    GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_1);

    ROM_GPIOPinConfigure(GPIO_PQ2_EPI0S22);
    GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_2);

    ROM_GPIOPinConfigure(GPIO_PQ3_EPI0S23);
    GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_3);

    ROM_GPIOPinConfigure(GPIO_PK7_EPI0S24);
    GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_7);

    ROM_GPIOPinConfigure(GPIO_PK6_EPI0S25);
    GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_6);

    ROM_GPIOPinConfigure(GPIO_PL4_EPI0S26);
    GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_4);

    ROM_GPIOPinConfigure(GPIO_PB2_EPI0S27); // A19
    GPIOPinTypeEPI(GPIO_PORTB_BASE, GPIO_PIN_2);


    //---------------------------------------------------------------
    // EPI Setup
    //---------------------------------------------------------------

    // Set the EPI divider.
    ROM_EPIDividerSet(EPI0_BASE, 0); // 20 MHz
    ROM_EPIDividerSet(EPI0_BASE, 1);


    // Select EPI Host Bus 8-bit mode.
    ROM_EPIModeSet(EPI0_BASE, EPI_MODE_HB8);

    // Configure SRAM mode
    // EPIConfigHB8Set - all data transfers use bits[7:0]
    ROM_EPIConfigHB8Set(EPI0_BASE, EPI_HB8_MODE_ADDEMUX | EPI_HB8_WRWAIT_0
    | EPI_HB8_RDWAIT_0 | EPI_HB8_CSCFG_CS, 0);

    // Set the address map. Base 0x6000 0000, Using 1MB out of 16MB addr space
    ROM_EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_16MB | EPI_ADDR_RAM_BASE_6);


    // Wait for the EPI initialization to complete.
    while(HWREG(EPI0_BASE + EPI_O_STAT) & EPI_STAT_INITSEQ)
    {
    }

  • Hello Joseph,

    And the schematics please!

    Regards
    Amit
  • Amit
    I cannot give you the schematic on this open forum - do you have a private address I can send it to. BTW, Kelvin has my email address.
    Joe
  • Thank you Amit for noting that the ROM_EPIDividerSet was erroneously set to zero. It is now set to 1 for a rate of 60 MHz.
    Technical Support from IAR noted: "Check that your debug probe is set up for that memory location. If you're using the I-jet you can go to the IDE menu bar and select I-jet/JTAGjet>>Memory Configuration. You may need to add this SRAM address block to the Used ranges window there." Now I am able to use the WATCH window for viewing external variables.