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TMS570LS3137 / TMS570LC4357 - test pin (ball U2)

Jiri Janacek
Genius 3315 points

Dear all,

following forum posts do clarify the function and recommend to pull down the TEST pin:

e2e.ti.com/.../360204
e2e.ti.com/.../235617

I would like to ask you whether a logical state of the TEST pin is somehow accessible for the user program? Is is possible to read the bit value from any register to check by the program that this pin is properly connected to the ground?

Many thanks in advance,

Best regards, Jiri

  • 0
    TI__Genius 11645 points
    Jiri,

    We certainly do not have any memory mapped register to read and check the value of the TEST pin.

    But can you explain us your concern a little more in detail ?
  • 0 in reply to KARTHIKEYAN RAJAMANICKAM
    Genius 3315 points

    Hello Karthik,

    our intention is to check the proper soldering of this pin to assure that this pin is really pulled down to the ground as the specification requires.

    As described in the above mentioned posts there could occurr a problem in environment with huge noise (that our application exactly is) if the TEST pin is not externally pulled down.

    Well, let me re-define my question - may the proper run of our application be influenced by the unconnected TEST pin? I expect (am afraid of)  the answer is - yes, it will be influenced for sure, even the application functionality will be interrupted / corrupted.

    Thank you very much in advance,

    Best regards, Jiri

  • 0 in reply to Jiri Janacek
    TI__Genius 11645 points
    Hi Jiri,

    Yeah we understand your concern.

    Is it your final application that you are concerned about ? what I meant to ask is that your debug interface will be in reset(nTRST) ?

    I remember we have another checkpoint after TEST which I'm not very sure, but will check and confirm that.
  • 0 in reply to KARTHIKEYAN RAJAMANICKAM
    Genius 3315 points
    Hello Karthik.

    I would try to specify the situation in more detail:
    Immediately after the PCB production the microcontroller is loaded by a test application which runs some HW specific tests to confirm the proper production of PCB, soldering, etc. Of course, this test application is loaded into flash via JTAG interface.
    There is no use of JTAG boundary scan.
    Maybe there is an issue that I do not understand the function of TEST pin - but honestly I should not, do not, even must not (TI internal) care :-) Is that somehow associated with the nTRST pin of JTAG interface? Logically there could be - TEST pin is mentioned in the Test & Debug signals within the datasheet.

    When I mentioned the application in the post above, I meant the application SW for real-world operation. Such application does not concern about TEST pin. But obviously the improper pull-down of TEST pin can disturb the run of the application SW as described in the device specification, right?

    Thanks a lot in advance,
    Best regards, Jiri
  • 0 in reply to Jiri Janacek
    TI__Guru 68920 points
    Jiri,

    No TEST has to do with factory test functions - not JTAG specifically (except in the sense that TEST must be low to use JTAG as well as any of the other documented features ... correctly).

    Are you actually seeing an issue, or are you just trying to prevent an issue based on the posts.
    I think the best practice would be either to leave the pin unconnected or to tie it externally to GND through a strong pulldown.

    The pin is not included on the boundary scan chain so there isn't even a way to test the connection to GND using boundary scan. I think you would have to add a test point and confirm that the pulldown current is within spec if you wanted to confirm the pin is soldered correctly.

    The 'huge noise' comment is a little too broad a statement to understand what the best option is going to be - I think we'd need to get into specifics about your env. in terms of understanding the frequencies / paths for noise injection and then debate whether it does more harm than good to add the external connection on TEST. My 2 cents anyway.

    -Anthony
  • 0 in reply to Anthony F. Seely
    Genius 3315 points
    Anthony, Karthik,

    thanks for your expert replies!

    Summary:
    - TEST pin cannot be accessed by any memory mapped register to be check by a test application;
    - if TEST pin is not pulled down correctly either in uC's internals and by an external resistor (in additioan) - it leads to an improper uC behaviour which will be recognized immediately.
    - Just a note: if TEST pin is not pulled down correctly either in uC's internals - it means that the chip of this uC has been damaged somehow - that can be got rid of;
    - anyway the TEST pin is externally pulled dowm in our design.

    Finally it is a bit more clear for me ;-)

    Thanks for your support,
    Jiri
  • 0 in reply to Jiri Janacek
    TI__Genius 11645 points
    Jiri,

    I just confirmed with our designers that TEST is qualified with nTRST as well. On your final application you will have the nTRST pin tied LOW , which gives a second level of protection.

    You are anyways recommended to Pull Down both of them if your final design, so you should be fine.