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TMS570 ECNT upper limit?

Joe Shidle
Intellectual 440 points

Other Parts Discussed in Thread: HALCOGEN, TMS570LS1224

Hi;


I'm setting up an N2HET pin on a TMS570LS1224 platform, using the ECNT feature.  I'm just using the HalCoGen generated edgeResetCounter() and  edgeGetCounter() APIs that access the pre-generated ECNT program.  See the code snippet at the bottom of this post for the ECNT code from het.c.

The VCLK2 is set to 80MHz and with an HR prescalar of 0, the HR clock is also running at 80MHz.  Using a function generator, I am able to measure input signals up to ~700kHz very accurately.  But that seems to be the break point, for any input signal over 700kHz results in a lower count, with the ECNT routine clearly missing edges.

I can't find anything in the TRM or otherwise that would indicate what the upper bound on the ECNT measurement would be, or a way to increase this "resolution".  I am not running anything else of note on the processor, all tasks are set to run idle loops while I was performing this experiment.

What is the upper limit on the ECNT measurement frequency?  If it is higher than 700kHz, how can I increase the performance of the ECNT, or otherwise use the N2HET functionality to measure input frequencies higher than 700kHz?

Thanks in advance,

Joe Shidle

----- ECNT code from HalCoGen het.c below ----

    /* ECNT: CCU Edge 0
    *         - Instruction                  = 17
    *         - Next instruction             = 18
    *         - Conditional next instruction = 18
    *         - Interrupt                    = 17
    *         - Pin                          = 4
    */
    {
        /* Program */
        0x00025440U,
        /* Control */
        (0x00024007U | (4U << 8U) | (2U << 4U)),
        /* Data */
        0x00000000U,
        /* Reserved */
        0x00000000U
    },

  • 0
    TI__Mastermind 49120 points
    Hi Joe,

    Can you confirm the LR prescaler that you are using? The ECNT instruction executes once every loop looking for a rising edge (in your code), so there can be only one rising edge in a loop. That essentially defines the fastest rate that input edges can occur on an input pin being measured by an ECNT instruction.

    You can look into using the PCNT or WCAP instructions for input period or pulse-width measurements. These instructions use the high-resolution clock as well, so the measurements can use the finer resolution available. The input timing requirements for these instructions are defined in the datasheet (SPNS190).

    Regards,
    Sunil
  • 0 in reply to Sunil Oak
    Intellectual 440 points
    Sunil;

    Thanks for the response.

    I currently have the LR set to 5 which (in HalCoGen) lists an "actual LR time" of 400ns. This would seem to indicate that the upper limit, of a once-per-loop measurement, would be 2.5MHz. Is this correct?

    I have read through SPNS190 but I can double-check that document.

    Thanks in advance,
    Joe Shidle
  • 0 in reply to Joe Shidle
    TI__Mastermind 49120 points
    Joe,

    LR of 5 means that the loop-resolution clock is running at 2.5MHz (80MHz / 32). Please also note that the ECNT instruction needs to "see" (happens once each LR clock) a "previous state" of "low" and a "new state" of "high" in order to detect a rising edge. Therefore the max frequency for a periodic input signal would be half of the LR clock frequency, which is 1.25MHz in your use case.

    Can you confirm the value stored in the HETPFR register after calling hetInit()?

    Regards,
    Sunil
  • 0 in reply to Sunil Oak
    Intellectual 440 points

    Sunil;


    I confirm that the HETPFR register is set to 0x00000500.


    I experimented a little with adjusting the LRPFC down to 4 (for 200ns loop) and confirmed that now my maximum resolution is higher, around 1.1MHz.


    Your response does answer the first half of my question, which was what the theoretical upper limit is, and that it's based on the loop resolution period.  Thank you.  I can work with this to determine my ideal max resolution and set the LRPFC accordingly.


    The other half of my question would be why, if the theoretical limit is 1.25MHz for a LRPFC of 5, I am seeing half that at ~700kHz.  Is it a question of MIPS / processor power? 

  • 0 in reply to Joe Shidle
    TI__Mastermind 49120 points
    Joe,

    Can you send me your CCS code project? It seems like there is a divide-by-2 enabled on the HCLK-->VCLK2-->HR clock -->LR clock path, which is not matching your configuration of 80MHz VCLK2, HR clock.

    That would explain your observation as well, as then the max input frequency for the ECNT to work correctly would be 625KHz.

    Regards,
    Sunil