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SSI (SPI)

Khatib Khatib
Prodigy 20 points

Hello evryone,

I am using a TM4C1294 launchPad, and i try to send a Signal with SSI peripheral from my computer to another devices, i wrote the Code for SPI and i tray to see the signal about a Oscilloscope but i see that no signal can send, can someone look my code and maeby see something that i not see. 

Thank you

This is a SPI part from my code

  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);

           SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2);


            GPIOPinConfigure(GPIO_PD3_SSI2CLK);
            GPIOPinConfigure(GPIO_PD2_SSI2FSS);
            GPIOPinConfigure(GPIO_PD1_SSI2XDAT0); // SSInXDAT0 functions as SSInTX
            GPIOPinConfigure(GPIO_PD0_SSI2XDAT1); //SSInXDAT1 functions as SSInRX


            GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_INT_PIN_2 | GPIO_PIN_3 );



            SSIConfigSetExpClk(SSI2_BASE, SysCtlClockGet(), Polarity,
                                SSI_MODE_MASTER, 1000000, length);

            //
            // Enable the SSI0 module.
            //
            SSIEnable(SSI2_BASE);

            SSIDataPut(SSI2_BASE, data);

regards

Khatib

  • 0
    TI__Guru**** 244400 points
    Hello Khatib

    SysCtlClockGet() is not applicable for TM4C129 devices. You would need to use the return value of SysCtlClockFreqSet to use as the system clock value. If you are using the default clock of PIOSC then you would need to hardcode the value of the System Clock to 16000000.

    Also please do make sure that before doing a SSIDataPut, you flush the RX FIFO by using SSIDataGet while there is Data in RX FIFO.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Guru 47900 points

    Hi Amit,

    Thanks for your excellent tip here.     Always helpful.

    My small tech firm still has (many) LM3S & LX4F boards in the field - and I'm (reasonably) certain - that at least for the LM3S (under StellarisWare) there was no such requirement to, "flush the RX FIFO by using SSIDataGet() prior to doing a, SSIDataPut."

    I'm embedded @ client now - yet I cannot recall that (same) requirement for our LX4F as well.     Might you comment?

    Is this advice (primarily - or "only") for TM4C129?      Thank you, Amit.

  • 0 in reply to cb1
    Expert 2415 points
    My understanding is that if you care about what you get back from the bus (ie. are not TX only), then the RX FIFO should be cleared prior to clocking to ensure you get the right byte out of the FIFO after you've done clocking - it shouldn't affect transmission per se. But I'm interested to hear whether there's something more behind that piece of advice...
  • 0 in reply to cb1
    TI__Guru**** 244400 points
    Hello cb1,

    The SysCtlClockGet would return the wrong value (and a terribly slow value) which will cause the configuration of the dividers to hang as it is trying to generate a fast clock from a slow clock (this is completely in the software and nothing to do with the hardware).

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Guru 47900 points

    Thanks both to Amit & Veikko.

    Recall that clients "demand" that our firm (only) employ the long past/proven StellarisWare - even w/123 devices.    (we've no interest in 129)

    I've never been a fan of employing a function (SysCtlClockGet()) to "process" when direct numeric entry is faster & results in less (unwanted) "adventure."    And to my best knowledge SysCtlClockGet() has no known flaws - under StellarisWare.

    Yet my question persists - is the "flush" of the RX FIFO required/recommended for non 129 devices?

    Again thanks.