TIVA EPI -DMA

Krishnan G Nair

Hello, I am trying this below code to transfer Data from EPI(C0000000) to sram memory.

I am able to debug it but its not writing any thing to memory.Any corrections to be made in code please suggest................

//*****************************************************************************

#include <stdio.h>

#include <stdint.h>

#include <stdlib.h>

#include <string.h>

#include <stdbool.h>

#include "inc/hw_types.h"

#include "inc/hw_epi.h"

#include "inc/hw_memmap.h"

#include "inc/hw_nvic.h"

#include "inc/hw_ints.h"

#include "inc/hw_uart.h"

#include "inc/hw_types.h"

#include "inc/hw_gpio.h"

#include "driverlib/flash.h"

#include "driverlib/gpio.h"

#include "drivers/pinout.h"

#include "driverlib/pin_map.h"

#include "driverlib/rom.h"

#include "driverlib/sysctl.h"

#include "driverlib/systick.h"

#include "driverlib/rom_map.h"

#include "driverlib/uart.h"

#include "driverlib/udma.h"

#include "utils/uartstdio.h"

#include "driverlib/epi.h"

#include "driverlib/flash.h"

#include "driverlib/interrupt.h"

#include "driverlib/debug.h"

#include "driverlib/rom_map.h"

#include "driverlib/timer.h"

#include "driverlib/rom_map.h"

#include "utils/ustdlib.h"

#include "drivers/pinout.h"

//*****************************************************************************

// Defines for setting up the system clock.

//*****************************************************************************

#define SYSTICKHZ 100

#define SYSTICKMS (1000 / SYSTICKHZ)

//*****************************************************************************

// The system clock frequency.

//*****************************************************************************

uint32_t g_ui32SysClock;

//*****************************************************************************

// The starting and ending address for the 8MB SDRAM chip (4Meg x 16bits) on

// the SDRAM daughter board.

//*****************************************************************************

#define SDRAM_START_ADDRESS 0x000000

#define SDRAM_END_ADDRESS 0x3FFFFF

//*****************************************************************************

// The control table used by the uDMA controller. This table must be aligned

// to a 1024 byte boundary.

//*****************************************************************************

#if defined(ewarm)

#pragma data_alignment=1024

unsigned char ucControlTable[1024];

#elif defined(ccs)

#pragma DATA_ALIGN(ucControlTable, 1024)

unsigned char ucControlTable[1024];

#else

unsigned char ucControlTable[1024] __attribute__ ((aligned(1024)));

#endif

//*****************************************************************************

// A pointer to the EPI memory aperture. Note that g_pusEPISdram is declared

// as volatile so the compiler should not optimize reads out of the image.

//*****************************************************************************

static volatile unsigned short *g_pusEPISdram;

//*****************************************************************************

// A global to hold the value to be transfered to the sdram.

//*****************************************************************************

static volatile unsigned short g_pusTxData[1];

//*****************************************************************************

// Variable to hold the count of the number of uDMA errors.

//*****************************************************************************

static volatile unsigned long g_uluDMAErrorCount;

//*****************************************************************************

// Variable to hold the count of the number of completed uDMA transfers.

//*****************************************************************************

static volatile unsigned long g_uluDMACompleted;

//*****************************************************************************

// This function sets up UART0 to be used for a console to display information

// as the example is running.

//*****************************************************************************

void

InitConsole(void)

{

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);

GPIOPinConfigure(GPIO_PA0_U0RX);

GPIOPinConfigure(GPIO_PA1_U0TX);

GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);

// Initialize the UART for console I/O.

UARTStdioConfig(0, 115200, g_ui32SysClock);

}

//*****************************************************************************

// The interrupt handler for uDMA errors. This interrupt will occur if the

// uDMA encounters a bus error while trying to perform a transfer. This

// handler just increments a counter if an error occurs.

//*****************************************************************************

void

uDMAErrorHandler(void)

{

unsigned long ulStatus;

// Check for uDMA error bit

ulStatus = uDMAErrorStatusGet();

// If there is a uDMA error, then clear the error and increment

// the error counter.

if(ulStatus)

{

uDMAErrorStatusClear();

g_uluDMAErrorCount++;

}

//*****************************************************************************

// Configure the uDMA transfers to the EPI sdram.

//*****************************************************************************

void

InitEPITransfer(void)

{

// Disable the attributes.

uDMAChannelAttributeDisable(UDMA_SEC_CHANNEL_EPI0TX,

UDMA_ATTR_ALTSELECT |

UDMA_ATTR_USEBURST |

UDMA_ATTR_HIGH_PRIORITY |

UDMA_ATTR_REQMASK);

uDMAChannelAttributeEnable(UDMA_SEC_CHANNEL_EPI0TX, UDMA_ATTR_USEBURST);

// Use the secondary channel - EPI0TX

uDMAChannelSelectSecondary(UDMA_DEF_TMR1B_SEC_EPI0TX);

// Setup the uDMA channel.

// Send 16-bit data, do not increment the source, increment the SDRAM

// memory by 16 bits, and by setting arbitration size to one the uDMA

// engine will rearbitrate after one item gets transfered.

uDMAChannelControlSet(UDMA_SEC_CHANNEL_EPI0TX,

UDMA_SIZE_16 |

UDMA_SRC_INC_NONE |

UDMA_DST_INC_16 |

UDMA_ARB_1);

}

//**************************************************************************

int CTI_EPI_Init() {

//**************** Enable EPI0********************//

SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);

//**************Configure EPIO********************//

EPIDividerSet(EPI0_BASE, 0);

EPIModeSet(EPI0_BASE, EPI_MODE_GENERAL);

EPIConfigGPModeSet(EPI0_BASE,

EPI_GPMODE_DSIZE_16 | EPI_GPMODE_ASIZE_12 | EPI_GPMODE_CLKPIN, 0,

0);

EPIAddressMapSet(EPI0_BASE, EPI_ADDR_PER_BASE_C | EPI_ADDR_PER_SIZE_64KB);

EPIFIFOConfig(EPI0_BASE,

(EPI_FIFO_CONFIG_TX_EMPTY | EPI_FIFO_CONFIG_RX_1_4

| EPI_FIFO_CONFIG_RSTALLERR));

IntEnable(INT_EPI0);

// Configure GPIO Ports and Pins

GPIOPinConfigure(GPIO_PB3_EPI0S28); //WR

GPIOPinConfigure(GPIO_PP2_EPI0S29); //RD

GPIOPinConfigure(GPIO_PK0_EPI0S0); //D0

GPIOPinConfigure(GPIO_PK1_EPI0S1); //D1

GPIOPinConfigure(GPIO_PK2_EPI0S2); //D2

GPIOPinConfigure(GPIO_PK3_EPI0S3); //D3

GPIOPinConfigure(GPIO_PC7_EPI0S4); //D4

GPIOPinConfigure(GPIO_PC6_EPI0S5); //D5

GPIOPinConfigure(GPIO_PC5_EPI0S6); //D6

GPIOPinConfigure(GPIO_PC4_EPI0S7); //D7

GPIOPinConfigure(GPIO_PA6_EPI0S8); //D8

GPIOPinConfigure(GPIO_PA7_EPI0S9); //D9

GPIOPinConfigure(GPIO_PG1_EPI0S10); //D10

GPIOPinConfigure(GPIO_PG0_EPI0S11); //D11

GPIOPinConfigure(GPIO_PM3_EPI0S12); //D12

GPIOPinConfigure(GPIO_PM2_EPI0S13); //D13

GPIOPinConfigure(GPIO_PM1_EPI0S14); //D14

GPIOPinConfigure(GPIO_PM0_EPI0S15); //D15

GPIOPinConfigure(GPIO_PL0_EPI0S16); //A0

GPIOPinConfigure(GPIO_PL1_EPI0S17); //A1

GPIOPinConfigure(GPIO_PL2_EPI0S18); //A2

GPIOPinConfigure(GPIO_PL3_EPI0S19); //A3

GPIOPinConfigure(GPIO_PQ0_EPI0S20); //A4

GPIOPinConfigure(GPIO_PQ1_EPI0S21); //A5

GPIOPinConfigure(GPIO_PQ2_EPI0S22); //A6

GPIOPinConfigure(GPIO_PQ3_EPI0S23); //A7

GPIOPinConfigure(GPIO_PK7_EPI0S24); //A8

GPIOPinConfigure(GPIO_PK6_EPI0S25); //A9

GPIOPinConfigure(GPIO_PL4_EPI0S26); //A10

GPIOPinConfigure(GPIO_PB2_EPI0S27); //A11

GPIOPinConfigure(GPIO_PP3_EPI0S30); //FRAME

GPIOPinConfigure(GPIO_PK5_EPI0S31); //CLK

GPIOPinTypeEPI(GPIO_PORTA_BASE, 0xC0);

GPIOPinTypeEPI(GPIO_PORTB_BASE, 0x0C);

GPIOPinTypeEPI(GPIO_PORTC_BASE, 0xF0);

GPIOPinTypeEPI(GPIO_PORTG_BASE, 0x03);

GPIOPinTypeEPI(GPIO_PORTK_BASE, 0xEF);

GPIOPinTypeEPI(GPIO_PORTL_BASE, 0x1F);

GPIOPinTypeEPI(GPIO_PORTM_BASE, 0x0F);

GPIOPinTypeEPI(GPIO_PORTP_BASE, 0x0C);

GPIOPinTypeEPI(GPIO_PORTQ_BASE, 0x0F);

GPIOPadConfigSet(GPIO_PORTA_BASE, 0xC0, GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD);

GPIOPadConfigSet(GPIO_PORTB_BASE, 0x0C, GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD);

GPIOPadConfigSet(GPIO_PORTC_BASE, 0xF0, GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD);

GPIOPadConfigSet(GPIO_PORTG_BASE, 0x03, GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD);

GPIOPadConfigSet(GPIO_PORTK_BASE, 0xEF, GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD);

GPIOPadConfigSet(GPIO_PORTL_BASE, 0x1F, GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD);

GPIOPadConfigSet(GPIO_PORTM_BASE, 0x0F, GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD);

GPIOPadConfigSet(GPIO_PORTP_BASE, 0x0C, GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD);

GPIOPadConfigSet(GPIO_PORTQ_BASE, 0x0F, GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD);

GPIODirModeSet(GPIO_PORTA_BASE, 0xC0, GPIO_DIR_MODE_HW);

GPIODirModeSet(GPIO_PORTB_BASE, 0x0C, GPIO_DIR_MODE_HW);

GPIODirModeSet(GPIO_PORTC_BASE, 0xF0, GPIO_DIR_MODE_HW);

GPIODirModeSet(GPIO_PORTG_BASE, 0x03, GPIO_DIR_MODE_HW);

GPIODirModeSet(GPIO_PORTK_BASE, 0xEF, GPIO_DIR_MODE_HW);

GPIODirModeSet(GPIO_PORTL_BASE, 0x1F, GPIO_DIR_MODE_HW);

GPIODirModeSet(GPIO_PORTM_BASE, 0x0F, GPIO_DIR_MODE_HW);

GPIODirModeSet(GPIO_PORTP_BASE, 0x0C, GPIO_DIR_MODE_HW);

GPIODirModeSet(GPIO_PORTQ_BASE, 0x0F, GPIO_DIR_MODE_HW);

return 0;

}

//***********Enable all GPIO BANKS**************//

CTI_EPI_Enable_GPIO_Bank() {

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM);

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOP);

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);

}

/***************Disable all unused Peripherals*******************/

void CTI_Disable_UnsedDev() {

SysCtlPeripheralDisable(SYSCTL_PERIPH_CAN0);

SysCtlPeripheralDisable(SYSCTL_PERIPH_CAN1);

SysCtlPeripheralDisable(SYSCTL_PERIPH_I2C0);

SysCtlPeripheralDisable(SYSCTL_PERIPH_I2C1);

SysCtlPeripheralDisable(SYSCTL_PERIPH_I2C2);

SysCtlPeripheralDisable(SYSCTL_PERIPH_I2C3);

SysCtlPeripheralDisable(SYSCTL_PERIPH_I2C4);

SysCtlPeripheralDisable(SYSCTL_PERIPH_I2C5);

SysCtlPeripheralDisable(SYSCTL_PERIPH_I2C6);

SysCtlPeripheralDisable(SYSCTL_PERIPH_I2C7);

SysCtlPeripheralDisable(SYSCTL_PERIPH_I2C8);

SysCtlPeripheralDisable(SYSCTL_PERIPH_I2C9);

SysCtlPeripheralDisable(SYSCTL_PERIPH_LCD0);

SysCtlPeripheralDisable(SYSCTL_PERIPH_SSI1);

SysCtlPeripheralDisable(SYSCTL_PERIPH_SSI2);

SysCtlPeripheralDisable(SYSCTL_PERIPH_SSI3);

SysCtlPeripheralDisable(SYSCTL_PERIPH_PWM0);

SysCtlPeripheralDisable(SYSCTL_PERIPH_PWM1);

SysCtlPeripheralDisable(SYSCTL_PERIPH_QEI0);

SysCtlPeripheralDisable(SYSCTL_PERIPH_QEI1);

SysCtlPeripheralDisable(SYSCTL_PERIPH_UART3);

SysCtlPeripheralDisable(SYSCTL_PERIPH_UART4);

SysCtlPeripheralDisable(SYSCTL_PERIPH_UART5);

SysCtlPeripheralDisable(SYSCTL_PERIPH_UART6);

SysCtlPeripheralDisable(SYSCTL_PERIPH_UART7);

SysCtlPeripheralDisable(SYSCTL_PERIPH_USB0);

SysCtlPeripheralDisable(SYSCTL_PERIPH_WDOG0);

SysCtlPeripheralDisable(SYSCTL_PERIPH_WDOG1);

SysCtlPeripheralDisable(SYSCTL_PERIPH_ADC0);

SysCtlPeripheralDisable(SYSCTL_PERIPH_ADC1);

SysCtlPeripheralDisable(SYSCTL_PERIPH_TIMER0);

SysCtlPeripheralDisable(SYSCTL_PERIPH_TIMER1);

SysCtlPeripheralDisable(SYSCTL_PERIPH_TIMER2);

SysCtlPeripheralDisable(SYSCTL_PERIPH_TIMER3);

SysCtlPeripheralDisable(SYSCTL_PERIPH_TIMER4);

SysCtlPeripheralDisable(SYSCTL_PERIPH_TIMER5);

SysCtlPeripheralDisable(SYSCTL_PERIPH_TIMER6);

SysCtlPeripheralDisable(SYSCTL_PERIPH_TIMER7);

SysCtlPeripheralDisable(SYSCTL_PERIPH_WTIMER0);

SysCtlPeripheralDisable(SYSCTL_PERIPH_WTIMER1);

SysCtlPeripheralDisable(SYSCTL_PERIPH_WTIMER2);

SysCtlPeripheralDisable(SYSCTL_PERIPH_WTIMER3);

SysCtlPeripheralDisable(SYSCTL_PERIPH_WTIMER4);

SysCtlPeripheralDisable(SYSCTL_PERIPH_WTIMER5);

}

//*****************************************************************************

// Configure EPI0 in SDRAM mode. The EPI memory space is setup using an a

// simple C array. This example shows how to read and write to an SDRAM card

// using the EPI bus in SDRAM mode.

//*****************************************************************************

int

main(void)

{

SysCtlMOSCConfigSet(SYSCTL_MOSC_HIGHFREQ);

// Set the device pinout appropriately for this board.

//PinoutSet();

// Run from the PLL at 120 MHz.

g_ui32SysClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |

SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480), 120000000);

// Set up the serial console to use for displaying messages. This is

// just for this example program and is not needed for EPI operation.

InitConsole();

CTI_EPI_Enable_GPIO_Bank();

CTI_Disable_UnsedDev();

UARTprintf("Initializing EPI\n");

CTI_EPI_Init();

// Enable the uDMA controller at the system level. Enable it to continue

// to run while the processor is in sleep.

SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);

// Enable the uDMA controller.

uDMAEnable();

// Point at the control table to use for channel control structures.

uDMAControlBaseSet(ucControlTable);

// Initialize the uDMA EPI transfers.

InitEPITransfer();

g_uluDMACompleted = 0;

g_uluDMAErrorCount = 0;

// Enable the uDMA controller error interrupt. This interrupt will occur

// if there is a bus error during a transfer.

IntEnable(INT_UDMAERR);

// Enable interrupts from the uDMA channel.

IntEnable(INT_UDMA);

// Enable processor interrupts.

IntMasterEnable();

// Set the EPI memory pointer to the base of EPI memory space. Note that

// g_pusEPISdram is declared as volatile so the compiler should not

// optimize reads out of the memory. With this pointer, the memory space

// is accessed like a simple array.

g_pusEPISdram = (unsigned short *)0xC0000000;

// Setup the data to send.

g_pusTxData[0] = 0xabcd;

// Print the start message.

UARTprintf(" SDRAM Write:\n");

UARTprintf(" Mem[0xC000.0000] <- 0xabcd\n\n");

UARTprintf("-------------------------------\n\n");

// Setup the uDMA transder to the SDRAM on the EPI bus. Send one *item*

// using basic mode.

uDMAChannelTransferSet(UDMA_SEC_CHANNEL_EPI0TX,

UDMA_MODE_BASIC,

(void *)g_pusTxData,

(void *)g_pusEPISdram,

1);

uDMAChannelEnable(UDMA_SEC_CHANNEL_EPI0TX);

// Check for the primary control structure to indicate complete or exit

// if an error occurs.

while((uDMAChannelModeGet(UDMA_DEF_TMR1B_SEC_EPI0TX) != UDMA_MODE_STOP) &&

(g_uluDMAErrorCount == 0))

{

}

// Check for an error.

if(g_uluDMAErrorCount == 0)

{

// Indicate a successful transfer.

g_uluDMACompleted++;

}

// Print out the results.

UARTprintf(" Mem[0xC000.0000] = 0x%4x\n\n", g_pusEPISdram[SDRAM_START_ADDRESS]);

UARTprintf("g_uluDMACompleted = %d\n\rg_uluDMAErrorCount = %d",

g_uluDMACompleted, g_uluDMAErrorCount);

// Done. Wait in a loop forever.

while(1)

{

}

/////////////////////////////////////////////////////////////

Regards,

Krishnan

over 10 years ago

0 Genatco over 10 years ago

Guru 56168 points

UARTprintf(" Mem[0xC000.0000] = 0x%4x\n\n", g_pusEPISdram[SDRAM_START_ADDRESS]);

Nice program - That address is a hex string array or integer based array?

Might UARTprintf be locking up at that point?

Perhaps a schematic of circuit would help to show in more detail how the EPI GPIO ports connect.
Another thing curios about, do EPI module assume high speed AHB ports by default?

0 Amit Ashara over 10 years ago

TI__Guru**** 244440 points

Hello Krishnan,

You are enabling the channel in Basic Mode which requires the EPI to generate a DMA Request. To be able to transfer data in such a scenario the Auto mode must be used with Software Channel Request. Please refer to the udma_demo example code on how to use it.

On the other hand if the EPI must issue a DMA Request then EPI must be configured to generate a DMA request using the Non Blocking Path for EPI which is mentioned well in the DMA operation section of EPI.

Regards
Amit

0 Genatco over 10 years ago in reply to Amit Ashara

Guru 56168 points

Krishnan stated he could debug code OK - would not the uDMA INT trigger an error in basic transfer mode?

Seems error INT might show up during stepping code in debug.

    // Enable the uDMA controller error interrupt.  This interrupt will occur
    // if there is a bus error during a transfer.
   
    IntEnable(INT_UDMAERR);

0 Amit Ashara over 10 years ago in reply to Genatco

TI__Guru**** 244440 points

Hello BP101

No. The DMA error will come only if the DMA gets a bus fault for wrong address space or restricted address space

Regards
Amit

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TIVA EPI -DMA