I am seeing a potential issue with the TMS570LS2124PGE revision C processor where a MibSPI5 transfer is not triggered when the trigger event and trigger source are set to falling edge and N2HET1[10], respectively. The same event and pin can, however, be used to trigger and ADC event group conversion.
In an attempt to get this to work, I jumped N2HET1[10] to GIOA[2]. Using HALCoGen 04.04.00, I left the ADC event group trigger set to N2HET1[10] falling edge, but I changed the MibSPI5 transfer group trigger source to GIOA[2]. The transfer group triggers as expected, as does the ADC event group. This leads me to believe there may be an issue with the MibSPI/N2HET triggering mechanism.
One other data point...
We use IAR Embedded Workbench as our IDE. Given my original setup (MibSPI5 transfer triggered from N2HET[10]), I noticed that if I halt at a breakpoint after all HALCoGen init() functions have been called and toggle the 8th bit in the HETDOUT register from 1 to 0, a MibSPI5 transfer is triggered.
I did not see anything in the errata document. Is there something I may be overlooking in my HALCoGen configuration? What additional information is needed for TI to investigate this potential issue?
Using HALCoGen 04.04.00, I have