Could not use the EMIF ( to avoid 3rd nWE pulse error) and FreeRTOS in RM48 at the same time?

In the case of 2th's experiment, If you do not use the FreeRTOS, it work normally in the MPU settings above.

I don't know what you want to change something.

my program map file show blow. I never execute from SDRAM(0x80000000). 

MEMORY CONFIGURATION

name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
VECTORS 00000000 00000020 00000020 00000000 X
KERNEL 00000020 00008000 00004840 000037c0 R X
FLASH0 00008020 00177fe0 0000d360 0016ac80 R X
FLASH1 00180000 00180000 00000000 00180000 R X
STACKS 08000000 00001500 00000000 00001500 RW
KRAM 08001500 00000800 0000016c 00000694 RW
RAM 08001d00 0003e300 0001442a 00029ed6 RW

I found out something.

I try to change the HalCoGen 04.04 to HalCoGen 04.02.

finally it isn't happen the prefetch error. but it is happen the data abort error when the RM48 access the EMIF Bus.

Additionally I should add to _mpuInit_() in sys_start.c. but it is happen the 3rd nWE pulse error. 

I need your help using the FreeRTOS and EMIF. 

From the memory map you shared, I do not see that you use external memory. Why do you think that EMIF causes the issue?

Thanks and regards,

Zhaohong

After I have solved the prefetch error. I change test program.
I already say that my target board have the Nor Flash and other controller IC.
and As you can see below, I should operate to read and write the Nor Flash or Controller IC in the FreeRTOS.
When I operate below the source, the value does not read exactly what i wrote.

//initchip_conf.h
/***********************
 * Basic I/O  Function *
 ***********************/

#define __DEF_IINCHIP_MAP_BASE_OFFSET__ 0x64800000 
 
uint16   IINCHIP_READ(uint32 addr)
{
#if (__DEF_IINCHIP_ADDRESS_MODE__ == __DEF_IINCHIP_DIRECT_MODE__)

	#ifdef __ADDRESS_ERROR__
		return (*((vuint16*)(__DEF_IINCHIP_MAP_BASE_OFFSET__+ addr*2)));
	#else
		return (*((vuint16*)(__DEF_IINCHIP_MAP_BASE_OFFSET__+ addr)));
	#endif

#else
      vuint16  data;  
      IINCHIP_CRITICAL_SECTION_ENTER(); 
      *((vuint16*)IDM_AR) = (uint16)addr;
      data = *((vuint16*)IDM_DR);   
      IINCHIP_CRITICAL_SECTION_EXIT();
      return data;
#endif
}
void     IINCHIP_WRITE(uint32 addr,uint16 data)
{
#if (__DEF_IINCHIP_ADDRESS_MODE__ == __DEF_IINCHIP_DIRECT_MODE__)
	#ifdef __ADDRESS_ERROR__
      (*((vuint16*)(__DEF_IINCHIP_MAP_BASE_OFFSET__ + addr*2))) = data;
	#else
      (*((vuint16*)(__DEF_IINCHIP_MAP_BASE_OFFSET__ + addr))) = data;
	#endif
#else
      IINCHIP_CRITICAL_SECTION_ENTER();
      *((vuint16*)IDM_AR) = addr;
      *((vuint16*)IDM_DR) = data;   
      IINCHIP_CRITICAL_SECTION_EXIT();

#endif   
}

//controlIC.c
/***********************
 * Basic I/O  Function *
 ***********************/
 
uint16   IINCHIP_READ(uint32 addr)
{
#if (__DEF_IINCHIP_ADDRESS_MODE__ == __DEF_IINCHIP_DIRECT_MODE__)

	#ifdef __ADDRESS_ERROR__
		return (*((vuint16*)(__DEF_IINCHIP_MAP_BASE_OFFSET__+ addr*2)));
	#else
		return (*((vuint16*)(__DEF_IINCHIP_MAP_BASE_OFFSET__+ addr)));
	#endif

#else
      vuint16  data;  
      IINCHIP_CRITICAL_SECTION_ENTER(); 
      *((vuint16*)IDM_AR) = (uint16)addr;
      data = *((vuint16*)IDM_DR);   
      IINCHIP_CRITICAL_SECTION_EXIT();
      return data;
#endif
}
void     IINCHIP_WRITE(uint32 addr,uint16 data)
{
#if (__DEF_IINCHIP_ADDRESS_MODE__ == __DEF_IINCHIP_DIRECT_MODE__)
	#ifdef __ADDRESS_ERROR__
      (*((vuint16*)(__DEF_IINCHIP_MAP_BASE_OFFSET__ + addr*2))) = data;
	#else
      (*((vuint16*)(__DEF_IINCHIP_MAP_BASE_OFFSET__ + addr))) = data;
	#endif
#else
      IINCHIP_CRITICAL_SECTION_ENTER();
      *((vuint16*)IDM_AR) = addr;
      *((vuint16*)IDM_DR) = data;   
      IINCHIP_CRITICAL_SECTION_EXIT();

#endif   
}


void     getSHAR(uint8 * addr)
{
   addr[0] = (uint8)(IINCHIP_READ(SHAR)>>8);
   addr[1] = (uint8)IINCHIP_READ(SHAR);
   addr[2] = (uint8)(IINCHIP_READ(SHAR2)>>8);
   addr[3] = (uint8)IINCHIP_READ(SHAR2);
   addr[4] = (uint8)(IINCHIP_READ(SHAR4)>>8);
   addr[5] = (uint8)IINCHIP_READ(SHAR4);
}
void     setSHAR(uint8 * addr)
{
   IINCHIP_WRITE(SHAR,(((uint16)addr[0])<<8)+addr[1]);
   IINCHIP_WRITE(SHAR2,((uint16)addr[2]<<8)+addr[3]);
   IINCHIP_WRITE(SHAR4,((uint16)addr[4]<<8)+addr[5]);
}

//.....


//test_task.c
	u32 s_ip, s_subnet,  s_gwip;
	uint8 s_mac[6];

	setSIPR((uint8 *)&tftp_cfg.ip);
	setSUBR((uint8 *)&tftp_cfg.subnet_mask);
	setSHAR((uint8 *)tftp_cfg.MAC);
	setGAR((uint8 *)&tftp_cfg.gwip);
	tftp_cfg.s =0;

	setIMR(0xC0FF); // socket0 interrupt enable and ipconfilct and destination port unreachable set
	printf("W5300 IMR = 0x%x\r\n", getIMR());
	printf("W5300 S0_IMR = 0x%x\r\n", getSn_IMR(0));
	printf("W5300 S1_IMR = 0x%x\r\n", getSn_IMR(1));


	//   view
	getSUBR((uint8 *)&s_subnet);
	getSHAR((uint8 *)s_mac);
	getSIPR((uint8 *)&s_ip);
	getGAR((uint8 *)&s_gwip);

	printf("--- W5300 information ---\r\n");
	printf("Sn_SSR = 0x%x\r\n", IINCHIP_READ(Sn_SSR(0)) );
	printf("Sn_IR = 0x%x\r\n", IINCHIP_READ(Sn_IR(0)) );
	printf("W5300 MR = 0x%x\r\n", getMR());
	printf("W5300 IDR = 0x%x\r\n", getIDR());

	printf("--- Network setting information ---\r\n");
	printf("[IP]          : %s\n", 	in_ntoa(s_ip));
	printf("[SERVER IP]   : %s\n", 	in_ntoa(tftp_cfg.serv_ip));
	printf("[GW IP]       : %s\n", 	in_ntoa(s_gwip));
	printf("[SUBNET MASK] : %s\n", 	in_ntoa(s_subnet));
	printf("[HW mac]      : 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 	s_mac[0], s_mac[1], s_mac[2], s_mac[3], s_mac[4], s_mac[5]);

In general, norflash and controller IC are hooked up as asynchronous external memory (address starts at 0x60000000). You cannot hook up norflash to SDRAM interface. You need to configure this region as "device" in order to write to them correctly. I do not see it in the Halcogen MPU configuration you shared in earlier post.

Thanks and regards,

Zhaohong

It seems that the Halcogen MPU configuration's picture is wrong. and the below picture is right. 

Of Course the experiments were carried out right the MPU setting value. 

Additionally I attached the Halcogen's files.

 

4760.halcogen_file.zip

I am waiting your support.