TM4C1294 SSI3 Issue

I am using the TM4C1294NCPDT and trying to use the SSI3 to control the external FLASH. But the initialize of SSI3 is always not exercise at all.  May someone help me to check this issue.

I set the CPU with 120MHz, enables UART and SSI2.

Codes are below.

static void ssi3Init_FLASH(void)
{
    uint32_t pui32RxData;

    //
    // Enable the SSI3 Peripheral used by the SPI_FLASH.
    //
    SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3);

    //
    // Configure GPIO Pins for UART SSI.
    //
    GPIOPinConfigure(GPIO_PQ2_SSI3XDAT0);
    GPIOPinConfigure(GPIO_PQ3_SSI3XDAT1);
    GPIOPinConfigure(GPIO_PF2_SSI3FSS);
    GPIOPinConfigure(GPIO_PF3_SSI3CLK);
    GPIOPinTypeSSI(GPIO_PORTQ_BASE,     GPIO_PIN_2 | GPIO_PIN_3);
    GPIOPinTypeSSI(GPIO_PORTF_AHB_BASE, GPIO_PIN_2 | GPIO_PIN_3);

    // Configure and enable the SSI port for SPI master mode. Use SSI3,
    // system clock supply, idle clock level low and active low clock in
    // freescale SPI mode, master mode, 1MHz SSI frequency, and 8-bit data.
    // For SPI mode, you can set the polarity of the SSI clock when the SSI
    // unit is idle. You can also configure what clock edge you want to
    // capture data on. Please reference the datasheet for more information on
    // the different SPI modes.
    SSIConfigSetExpClk(SSI3_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0,
    SSI_MODE_MASTER, 70000000, 8);

    //Enable
    SSIEnable(SSI3_BASE);

    // Read any residual data from the SSI port.  This makes sure the receive
    // FIFOs are empty, so we don't read any unwanted junk.  This is done here
    // because the SPI SSI mode is full-duplex, which allows you to send and
    // receive at the same time.  The SSIDataGetNonBlocking function returns
    // "true" when data was returned, and "false" when no data was returned.
    // The "non-blocking" function checks if there is any data in the receive
    // FIFO and does not "hang" if there isn't.
    //
    while(SSIDataGetNonBlocking(SSI3_BASE, &pui32RxData))
    {
    }
}