• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 32 subscribers
  • Views 745 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570 HETGCR

Alex Spivak
Intellectual 930 points
Other Parts Discussed in Thread: HALCOGEN

In TMS570LS31x HETGCR register bit 24 (HET PIN ENA) always reads zero even if the bit is set to 1. In TRM the bit is defined as R/W-1 , which means that the value after reset should be 1. Is there a mistake in the TRM?

  • 0
    TI__Mastermind 49120 points
    Alex,

    The N2HET1_PIN_nDIS input to the N2HET1 module comes from the GIOA[5] pin. This input needs to be High for the PIN_ENA to come up as set by default. GIOA[5] has a default pull-down on it and hence drives the PIN_nDIS input low to the N2HET1 module.

    So the TRM needs to be updated to include the statement that this bit's default state depends on the default state of the PIN_nDIS input to the N2HET module.

    Also, in order to set this bit in the HETGCR register, you need to enable a pull-up on the GIOA[5] pin using the pull-select register (PSEL) in the GIO module.

    Regards,
    Sunil
  • 0 in reply to Sunil Oak
    Intellectual 930 points
    OK, thanks Sunil. I don't use this feature, so I don't need to set this bit. Originally I thought that I have to set this bit to enable the output buffer for those HET pins that that are set for output, but if I don't use HETPINDIS.x, the HETDIR.x will enable the output buffer for the output pins.
    Alex
  • 0 in reply to Alex Spivak
    TI__Mastermind 49120 points
    Alex,

    That's right. Essentially when this feature is required, the GIOA[5] input must be driven/pulled high by default in order for the application to enable this feature. In fact, we should rename the bit 24 to better reflect its functionality. I will take this up internally and suggest the required updates to the TRM.

    Regards,
    Sunil
  • 0 in reply to Sunil Oak
    TI__Genius 14205 points
    Hi All,

    From HALCoGen point of view in future release ( from 4.05.xx) we will add options in HET Tab to enable/disable the PINnDIS feature.
  • 0 in reply to Prathap
    TI__Guru 68950 points

    Ok  let's not change the bit name though - since the name isn't 'wrong' it just could have been named more precisely.   Too many ripple effects and it'll cause confusion to have one name in some places and another name in others.

    I'd focus on improving descriptions of what the bit does instead - whether that is in the graphical representation on the HalCoGen tab or in the TRM chapter.