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Problem when initializing the FIQ Banked register



Hello,

I use the following code to initialize the FIQ Banked register.

             ;Initialization of fiq Time Out interrupt routine                        

;------------------------------------------------

       cps    #fiq_Mode           ;Switch to FIQ mode (M = 10001)

       ldr    R8,$ScheStacktop    ;R8_fiq = Top of the schedulers stacks

       movr32 R9,#taskToutFrCt    ;R9_fiq = address of the free running counter

       cps    #user_Mode          ;Switch to System Mode (M = 11111)

$ScheStacktop .word       spScheduler01 ;Top of the scheduler stack

 This code works well with R4F processor.

But with R5F processor the value of the FIQ banked register disappear when the processor return in user mode.

Where is the problem?

Thanks a lot for your help

Jerome

  • Hello Jerome,

      The R4 and R5 archiecture are the same in this regard. Not sure what you meant by the FIQ banked registers disappear when you are in user mode. The FIQ banked registers are accessible when you are in FIQ mode. When you switch from user mode to FIQ mode, do you see these banked registers with the intended values?

  • Hello Charles,

    Thanks for your help. In fact it’s not during the initialization phase that the FIQ Banked registers are lost but between the end of the initialization and the first FIQ Interrupt. There is no cps instruction during this phase. So I don’t know what can change the value of FIQ Banked register. The different values are the following:

    R4F Behavior
    ---------------------------------

    before FIQ initialization  

    R8 = 0   R9 =  0  

    after FIQ initialisation before return to cps

     R8 = 0x08002F00  R9 = 0xFFFFFC10

    At the beginning of the first interrupt FIQ 

    R8 = 0x08002F00 R9 = 0xFFFFFC10  

     

    R5F Behavior
    ---------------------

    before FIQ initialization

     Core Register  FIQ Register (visible in CCS FIQ_Registers) 
     R8= 0  R9=0

    after FIQ initialisation before return to cps user Mode

     R8 = 0x08002F00  R9 =0xFFFFFC10

    At the beginning of the first interrupt FIQ  

    R8 = 0x00000023 R9 = 0x00000001 

    Kind Regards

    Jerome

  • Hello Charles,
    The problem come from the fact that just after enabling the firq interrupt an interrupt from HCG (mibspiInit() occurs to initialize mibspi. And that subroutine change the Fiq banked registers. I find it in the following trace:


    initialiseIT() MOV R0, #0
    initialiseIT() CPS #18
    initialiseIT() STMFD R13!, {R0}
    initialiseIT() STMFD R13!, {R0}
    initialiseIT() STMFD R13!, {R0}
    initialiseIT() CPS #31
    initialiseIT() CPS #17
    initialiseIT() LDR R8, 0x8064
    initialiseIT() MOVW R9, #64528
    initialiseIT() MOVT R9, #65535
    initialiseIT() CPS #31
    initialiseIT() BX R14
    main_.asm: CPSIE f, ;Enable FIQ Interrupt
    mibspiInit() LDR PC, 0xFFFFFE74 ;HCG Subroutine to initialize mibspi


    Kind Regards
  • Hello Jerome,

      Glad that you found the root cause.

  • Hello Charles,
    In fact the problem comes from the “esmHighInterrupt” subroutine generated by HCG.
    I don’t know why but the Function:string column of trace analyzer give sometime a wrong information.
    The “esmHighInterrupt” subroutine doesn’t save the FIQ banked registers.
    So I fixed the issue by modifying the “esmHighInterrupt” subroutine :

    I wrote two assembly functions in an interrupt.asm file
    And I called these functions in “esmHighInterrupt” subroutine

    Kind regards

    ;SAVE ALL REGISTERS TO INCLUDE IN HCG INTERRUPTS SUBROUTINE
    ;----------------------------------------------------------
    saveAllReg push {r4,r5,r6,r7,r8,r9,r10,r11}
    bx r14

    ;RESTORE ALL REGISTERS TO INCLUDE IN HCG INTERRUPTS SUBROUTINE
    ;-------------------------------------------------------------
    restrAllReg pop {r4,r5,r6,r7,r8,r9,r10,r11}
    bx r14


    The following modifications save and restore registers in the esmHighInterrupt in HL_esm.c file

    void saveAllReg(void);
    void restrAllReg(void);

    void esmHighInterrupt(void)
    {
    /* Note : Group 1 Error */
    /* 1 to 32 -> channel 0 to 31 */
    /* 65 to 96 -> channel 32 to 63 */
    /* 129 to 160 -> channel 64 to 95 */
    /* Note : Group 2 Error */
    /* 33 to 64 -> channel 0 to 31 */
    saveAllReg();

    uint32 vec = esmREG->IOFFHR - 1U;

    /* USER CODE BEGIN (50) */
    /* USER CODE END */

    if (vec < 32U)
    {
    esmREG->SR1[0U] = (uint32)1U << vec;
    esmGroup1Notification(esmREG,(vec));
    }
    else if (vec < 64U)
    {
    esmREG->SR1[1U] = (uint32)1U << (vec-32U);
    esmGroup2Notification(esmREG,(vec-32U));
    }
    else if (vec < 96U)
    {
    esmREG->SR4[0U] = (uint32)1U << (vec-64U);
    esmGroup1Notification(esmREG,(vec-32U));
    }
    else if ((vec >= 128U) && (vec < 160U))
    {
    esmREG->SR7[0U] = (uint32)1U << (vec-128U);
    esmGroup1Notification(esmREG,(vec-96U));
    }
    else
    {
    esmREG->SR7[0U] = 0xFFFFFFFFU;
    esmREG->SR4[1U] = 0xFFFFFFFFU;
    esmREG->SR4[0U] = 0xFFFFFFFFU;
    esmREG->SR1[1U] = 0xFFFFFFFFU;
    esmREG->SR1[0U] = 0xFFFFFFFFU;
    }

    /* USER CODE BEGIN (51) */
    restrAllReg();
    /* USER CODE END */
    }

    The resulting trace is the following:

    Function:string Disassembly:string Source:string
    Enable_Fiq CPSIE f
    Vector FIQ LDR PC, 0xFFFFFE74 ldr pc,[pc,#-0x1b0] Fetch FIQ vector
    esmHighInterrupt STMFD R13!, {R0, R1, R2, R3, R12, R14}
    esmHighInterrupt VMRS R12, FPEXC
    esmHighInterrupt STMFD R13!, {R12}
    esmHighInterrupt VMRS R12, FPSCR
    esmHighInterrupt STMFD R13!, {R12}
    esmHighInterrupt VSTMDB R13!, {D0-D7}
    esmHighInterrupt SUB R13, R13, #8
    saveAllReg() BL 0x5F14
    saveAllReg() STMFD R13!, {R4, R5, R6, R7, R8, R9, R10, R11} "saveAllReg push {r4,r5,r6,r7,r8,r9,r10,r11}"
    saveAllReg() BX R14 " bx r14"
    esmHighInterrupt LDR R8, 0x6230
    esmHighInterrupt LDR R8, [R8]
    esmHighInterrupt SUB R8, R8, #1
    esmHighInterrupt STR R8, [R13]
    esmHighInterrupt LDR R8, [R13]
    esmHighInterrupt CMP R8, #32
    esmHighInterrupt BCS 0x611C
    esmHighInterrupt LDR R8, [R13]
    esmHighInterrupt CMP R8, #64
    esmHighInterrupt BCS 0x6154
    esmHighInterrupt LDR R8, [R13]
    esmHighInterrupt LDR R10, 0x623C
    esmHighInterrupt MOV R9, #1
    esmHighInterrupt SUB R8, R8, #32
    esmHighInterrupt MOV R8, R9, LSL R8
    esmHighInterrupt STR R8, [R10]
    esmHighInterrupt LDR R8, [R13]
    esmHighInterrupt LDR R0, 0x6238
    esmHighInterrupt SUB R1, R8, #32
    esmHighInterrupt BL 0x55D0
    esmGroup2Notificat SUB R13, R13, #8 {
    esmGroup2Notificat STR R1, [R13, #4]
    esmGroup2Notificat STR R0, [R13]
    esmGroup2Notificat ADD R13, R13, #8 }
    esmGroup2Notificat BX R14
    esmHighInterrupt B 0x620C
    restrAllReg() BL 0x5F1C
    restrAllReg() LDMFD R13!, {R4, R5, R6, R7, R8, R9, R10, R11} "restrAllReg pop {r4,r5,r6,r7,r8,r9,r10,r11}"
    restrAllReg() BX R14 " bx r14"
    esmHighInterrupt ADD R13, R13, #8
    esmHighInterrupt VMOV R0, R13, D0
    esmHighInterrupt LDMFD R13!, {R12}
    esmHighInterrupt VMSR FPSCR, R12
    esmHighInterrupt LDMFD R13!, {R12}
    esmHighInterrupt VMSR FPEXC, R12
    esmHighInterrupt LDMFD R13!, {R0, R1, R2, R3, R12, R14}
    esmHighInterrupt SUBS PC, R14, #4 " SUBS PC, R14, #4 ;Do return from exception"
    main_.asm: CPSIE i, " Enable_Irq"