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TMS470R1B1M sample programs / GEL file

pramodbk
Prodigy 220 points
Other Parts Discussed in Thread: TMS470R1B1M

Hi,

I have recently got a TMS470R1B1M board and I was able to connect this board using CCS3.3 and XDS510 JTAG . But I am not able to access the internal RAM or any of the registers. Can someone help me with a GEL file or some kind of sample program which can help me in getting started.

Regards,
Pramod

  • 0
    TI__Genius 13810 points

    Pramod,

    Please be aware that the TMS470R1 Series (including the TMS470R1B1M device) is not recommended for new designs. However, the device, tool, or software continues to be in production to support existing customers.  Please see the full 'NRDN' notice here.

    Soon TI will be launching the new TMS470M series of microcontrollers.  This series will feature greater ARM CPU performance and a similar peripherial set to the TMS470R1 Series of microcontrollers.  Please come back soon for more information about the TMS470M Series of microcontrollers.  The product preview for the first two microcontrollers in the TMS470M series is available here: TMS470MF0660x - SPNS157. 

    Now, to answer your origional question; to access the internal RAM, you have to set up the memory map first. Information about memory map is available in http://focus.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=spnu189h&fileType=pdf. You should be able to access the system registers and CPU registers. You can only access the peripherals registers after you enable the Peripherals.

    Here is some example code during device initialization

     e_DEC_ST is located at 0xFFFFFE00. e_MMC_ST is located at 0xFFFFFD00. e_CIM_ST is located at 0xFFFFFF20.

    void dev_init(void)
    { 

      asm("  mov r9, lr");
     e_SYS_ST.GlbCtrl_UW=0x09; /* SYSCLK = OSCIN * 4/2 */
     e_SYS_ST.SysESR_UW = 0x00; /* clear System Reset Status */                                   
     
     e_DEC_ST.mfbalR0_UW = 0x000; /* Clear Memory Map */
     e_DEC_ST.mfbalR1_UW = 0x000;
     e_DEC_ST.mfbalR2_UW = 0x000;
     e_DEC_ST.mfbalR3_UW = 0x000;
     e_DEC_ST.mfbalR4_UW = 0x000;
     e_DEC_ST.mfbalR5_UW = 0x000;
     e_DEC_ST.mfbahR0_UW = 0x000;
     e_DEC_ST.mfbahR1_UW = 0x000;
     e_DEC_ST.mfbahR2_UW = 0x000;
     e_DEC_ST.mfbahR3_UW = 0x000;
     e_DEC_ST.mfbahR4_UW = 0x000;
     e_DEC_ST.mfbahR5_UW = 0x000;
     
     e_DEC_ST.mfbahR2_UW = 0x100;
     e_DEC_ST.mfbalR2_UW = 0x070; /* Memory: RAM 64K at 0x0100_0000 */

     e_DEC_ST.mfbalR0_UW = 0x0b2; /* Memory: Flash 1024K at 0x0000_0000 */
     e_DEC_ST.mfbalR0_UW |= 0x100;
     
     e_MMC_ST.pcr0_UN.pcr0_UW = 0x0001;  /* ICLK = SYSCLK/1, Peripherals enabled */
     e_CIM_ST.Reqmask_UL = 0x0000;  /* No interrupts */
     e_CIM_ST.Firqpr_UL  = 0x0000;  /* All Interrupts IRQ */

     asm(" bx r9");
    }

    Regards,

    Haixiao

  • 0 in reply to Haixiao Weng
    Prodigy 220 points

    Haixiao,

    Thanks for the detailed reply. Now I am able to access the peripheral registers without any issues, but still having issues in accessing the internal RAM. I have used the same code that  you had sent me, but I added a few lines. I have added dummy read to the registers 0xFFEE, 0xFFE4, 0xFFE8 & 0xFFEC. Could you please comment on the configurations below. I have set the required configurations, but the RAM is still not accessible.

     

     unsigned int read = 0;

       /* Dummy read of MSM password location */
      read = (*(int *) 0xFFE0);
      read = (*(int *) 0xFFE4);
      read = (*(int *) 0xFFE8);
      read = (*(int *) 0xFFEC);

      *(unsigned int *)GLBCTRL =0x09;  /* SYSCLK = OSCIN * 4/2 */
      *(unsigned int *)SYSESR  =0; /* clear System Reset Status */    

      /* Initializes the system module for all x10 and x05. */
     
      clear_memory_map();

      map_ram();

    }


    clear_memory_map()
    {
      *(unsigned int *)MFBALR0  = 0x00000000;               /* Enable the memory map           */
      *(unsigned int *)MFBAHR0  = 0x00000000;                /* int FLASH/boot FLASH/R0M        */
      *(unsigned int *)MFBALR1  = 0x00000000;                /* Block size is 0 Kb               */
      *(unsigned int *)MFBAHR1  = 0x00000000;                /* Starting address is 0x0000       */
      *(unsigned int *)MFBALR2  = 0x00000000;                /* Block size is 8 Kb               */
      *(unsigned int *)MFBAHR2  = 0x00000000;                /* Starting address is 0x0000       */
      *(unsigned int *)MFBALR3  = 0x00000000;                /* Block size is 0 Kb               */
      *(unsigned int *)MFBAHR3  = 0x00000000;                /* Starting address is 0x0000       */
      *(unsigned int *)MFBALR4  = 0x00000000;                /* Block size is 2 Kb                                    */
      *(unsigned int *)MFBAHR4  = 0x00000000;                /* Starting address is 0x00100000                       */
      *(unsigned int *)MFBALR5  = 0x00000000;                /* Block size is 0 Kb                                    */
      *(unsigned int *)MFBAHR5  = 0x00000000;                /* Starting address is 0x0000                            */
    }

    map_ram()
    {
      *(unsigned int *)MFBALR0 = 0x00000000;                /* Enable the memory map block size is 128K                */
      *(unsigned int *)MFBALR1 = 0x00000000;                /* Block size is 0 Kb                                    */
      *(unsigned int *)MFBALR2 = 0x00000000;                /* Block size is 0 Kb                                    */
      *(unsigned int *)MFBALR3 = 0x00000000;                /* Block size is 0 Kb                                    */
      *(unsigned int *)MFBALR4 = 0x00000000;                /* Block size is 0 Kb                                    */
      *(unsigned int *)MFBALR5 = 0x00000000;                /* Block size is 0 Kb                                    */

      *(unsigned int *)MFBAHR2  = 0x00000100;                /* Starting address is 0x1000000                            */
      *(unsigned int *)MFBALR2  = 0x00000070;                /* Block size is 64 Kb                                    */
      *(unsigned int *)MFBALR0 |= 0x00000100;               /* Enable the memory map                                */
      *(unsigned int *)PCR0     = 0x03;                                     /* ICLK = SYSCLK/2, Peripherals enabled */
      *(unsigned int *)SMCR1    = 0x00000072;                /* Static Memory Control Register 0 . Setting the wait states*/
    }

     

    Regards,

    Pramod

  • 0 in reply to pramodbk
    TI__Genius 13810 points

    Pramod,

    I don't see any problem in your code.

    Try this:

    Connect to the CCS, open the memory window @ 0xFFFFFE00 and another memory window @ 0x04000000

    1.       SET 0xFFFFFE04 to 0x0 if it is not 0

    2.       SET 0xFFFFFE10 to 0x100

    3.       SET 0xFFFFFE14 to 0x70

    4.       SET 0xFFFFFE04 to 0x100

    Refresh both memory windows.

    Regards,

    Haixiao

  • 0 in reply to Haixiao Weng
    Prodigy 220 points

    Haixiao,

    Finally it worked. The main issue is that I had to do a memory mapping for the Internal SRAM in the CCS. This way I had to inform the CCS that the SRAM area is a Read/Write area. Once I did this, I am able to read/write to the SRAM. So basically as you had mentioned, there was no problem with my code. Thanks for all the support.

    Regards,

    Pramod