PWM0 GEN0 Interrupt ADC on count zero & CCS Debug show Interrupt Comp A up?

Version: TivaWare_C_Series-2.1.0.12573

Checking the PWM peripheral configuration in CCS debug reveals GEN0 trigger & interrupt enables are not being configured properly to the reset defaults.

Why is this happening?

// Configure PWM Generators:

    ROM_PWMGenIntTrigEnable(PWM0_BASE, PWM_GEN_1, PWM_INT_CNT_ZERO | PWM_TR_CNT_LOAD); 

//*****************************************************************************
//
// Defines for enabling, disabling, and clearing PWM generator interrupts and
// triggers.
//
//*****************************************************************************
#define PWM_INT_CNT_ZERO        0x00000001  // Int if COUNT = 0
#define PWM_INT_CNT_LOAD        0x00000002  // Int if COUNT = LOAD
#define PWM_INT_CNT_AU          0x00000004  // Int if COUNT = CMPA U
#define PWM_INT_CNT_AD          0x00000008  // Int if COUNT = CMPA D
#define PWM_INT_CNT_BU          0x00000010  // Int if COUNT = CMPB U
#define PWM_INT_CNT_BD          0x00000020  // Int if COUNT = CMPB D
#define PWM_TR_CNT_ZERO         0x00000100  // Trig if COUNT = 0
#define PWM_TR_CNT_LOAD         0x00000200  // Trig if COUNT = LOAD
#define PWM_TR_CNT_AU           0x00000400  // Trig if COUNT = CMPA U
#define PWM_TR_CNT_AD           0x00000800  // Trig if COUNT = CMPA D
#define PWM_TR_CNT_BU           0x00001000  // Trig if COUNT = CMPB U
#define PWM_TR_CNT_BD           0x00002000  // Trig if COUNT = CMPB D