Hello,
I am using the TMDXRM57LHDK Dev Board with HCG and the CCS Version: 6.1.0.00104.
With HCG nothing has been activated in ESM module.
Just after enabling FIQ an interrupt occurs and calls the “esmHighInterrupt” subroutine located in HL_esm.c file. How that can be possible?
The ESM1 registers values at the beginning of the “esmHighInterrupt” subroutine are listed at the end of the message.
The trace at the beginning of the “esmHighInterrupt” subroutine are also listed at the end of the message.
With CCS, when I look at the registers I can see ESM1 and ESM2 registers. In RM57L843 documentation there is only one group of ESM register. What about the ESM2 registers?
We can see the Stat2 register = 8. I suppose it corresponds to channel 3. But It’s difficult for me to find at which element of the device the channel 3 is affected. With HCG I see it corresponds to DMA ECC UERR. Is that correct?
Thanks for your help
Kind regards
Jerome
IflErrPinSet1 0x00000000 Influence Error Pin Set/Status Register 1 [Memory Mapped]
IflErrPinClr1 0x00000000 Influence Error Pin Clear/Status Register 1 [Memory Mapped]
IntEnaSet1 0x00000000 Interrupt Enable Set/Status Register 1 [Memory Mapped]
IntEnaClr1 0x00000000 Interrupt Enable Clear/Status Register 1 [Memory Mapped]
IntLvlSet1 0x00000000 Interrupt Level Set/Status Register 1 [Memory Mapped]
IntLvlClr1 0x00000000 Interrupt Level Clear/Status Register 1 [Memory Mapped]
Stat1 0x00000000 Status Register 1 [Memory Mapped]
Stat2 0x00000008 Status Register 2 [Memory Mapped]
Stat3 0x00000000 Status Register 3 [Memory Mapped]
ErrPinStat 0x00000000 Error Pin Status Register [Memory Mapped]
IntOffstHgh 0x00000024 Interrupt Offset High Register [Memory Mapped]
IntOffstLow 0x00000000 Interrupt Offset Low Register [Memory Mapped]
LtCnt 0x00000000 Low-Time Counter Register [Memory Mapped]
LtCntPre 0x00003FFF Low-Time Counter Preload Register [Memory Mapped]
ErrKey 0x00000000 Error Key Register [Memory Mapped]
ShdwStat2 0x00000008 Status Shadow Register [Memory Mapped]
IflErrPinSet4 0x00000000 Influence Error Pin Set/Status Register 4 [Memory Mapped]
IflErrPinClr4 0x00000000 Influence Error Pin Clear/Status Register 4 [Memory Mapped]
IntEnaSet4 0x00000000 Interrupt Enable Set/Status Register 4 [Memory Mapped]
IntEnaClr4 0x00000000 Interrupt Enable Clear/Status Register 4 [Memory Mapped]
IntLvlSet4 0x00000000 Interrupt Level Set/Status Register 4 [Memory Mapped]
IntLvlClr4 0x00000000 Interrupt Level Clear/Status Register 4 [Memory Mapped]
Stat4 0x00000000 Status Register 4 [Memory Mapped]
Stat5 0x00000000 Status Register 5 [Memory Mapped]
Stat6 0x00000000 Status Register 6 [Memory Mapped]
ShdwStat5 0x00000000 Status Shadow Register5 [Memory Mapped]
IflErrPinSet7 0x00000000 Influence Error Pin Set/Status Register 7 [Memory Mapped]
IflErrPinClr7 0x00000000 Influence Error Pin Clear/Status Register 7 [Memory Mapped]
IntEnaSet7 0x00000000 Interrupt Enable Set/Status Register 7 [Memory Mapped]
IntEnaClr7 0x00000000 Interrupt Enable Clear/Status Register 7 [Memory Mapped]
IntLvlSet7 0x00000000 Interrupt Level Set/Status Register 7 [Memory Mapped]
IntLvlClr7 0x00000000 Interrupt Level Clear/Status Register 7 [Memory Mapped]
Stat7 0x00000000 Status Register 7 [Memory Mapped]
Stat8 0x00000000 Status Register 8 [Memory Mapped]
Stat9 0x00000000 Status Register 9 [Memory Mapped]
ShdwStat8 0x00000000 Status Shadow Register8 [Memory Mapped]
IflErrPinSet10 0x00000000 Influence Error Pin Set/Status Register 10 [Memory Mapped]
IflErrPinClr10 0x00000000 Influence Error Pin Clear/Status Register 10 [Memory Mapped]
IntEnaSet10 0x00000000 Interrupt Enable Set/Status Register 10 [Memory Mapped]
IntEnaClr10 0x00000000 Interrupt Enable Clear/Status Register 10 [Memory Mapped]
IntLvlSet10 0x00000000 Interrupt Level Set/Status Register 10 [Memory Mapped]
IntLvlClr10 0x00000000 Interrupt Level Clear/Status Register 10 [Memory Mapped]
Stat10 0x00000000 Status Register 10 [Memory Mapped]
Stat11 0x00000000 Status Register 11 [Memory Mapped]
Stat12 0x00000000 Status Register 12 [Memory Mapped]
ShdwStat11 0x00000000 Status Shadow Register11 [Memory Mapped]
The trace after enabling FIQ is the folowing:
Function:string Disassembly:string Source:string
Enable_Fiq CPSIE f
Vector FIQ LDR PC, 0xFFFFFE74 ldr pc,[pc,#-0x1b0] Fetch FIQ vector
esmHighInterrupt STMFD R13!, {R0, R1, R2, R3, R12, R14}
esmHighInterrupt VMRS R12, FPEXC
esmHighInterrupt STMFD R13!, {R12}
esmHighInterrupt VMRS R12, FPSCR
esmHighInterrupt STMFD R13!, {R12}
esmHighInterrupt VSTMDB R13!, {D0-D7}
esmHighInterrupt SUB R13, R13, #8
esmHighInterrupt LDR R8, 0x6230
esmHighInterrupt LDR R8, [R8]
esmHighInterrupt SUB R8, R8, #1
esmHighInterrupt STR R8, [R13]
esmHighInterrupt LDR R8, [R13]
esmHighInterrupt CMP R8, #32
esmHighInterrupt BCS 0x611C
esmHighInterrupt LDR R8, [R13]
esmHighInterrupt CMP R8, #64
esmHighInterrupt BCS 0x6154
esmHighInterrupt LDR R8, [R13]
esmHighInterrupt LDR R10, 0x623C
esmHighInterrupt MOV R9, #1
esmHighInterrupt SUB R8, R8, #32
esmHighInterrupt MOV R8, R9, LSL R8
esmHighInterrupt STR R8, [R10]
esmHighInterrupt LDR R8, [R13]
esmHighInterrupt LDR R0, 0x6238
esmHighInterrupt SUB R1, R8, #32
esmHighInterrupt BL 0x55D0
esmGroup2Notificat SUB R13, R13, #8 {
esmGroup2Notificat STR R1, [R13, #4]
esmGroup2Notificat STR R0, [R13]
esmGroup2Notificat ADD R13, R13, #8 }
esmGroup2Notificat BX R14
esmHighInterrupt B 0x620C
esmHighInterrupt ADD R13, R13, #8
esmHighInterrupt VMOV R0, R13, D0
esmHighInterrupt LDMFD R13!, {R12}
esmHighInterrupt VMSR FPSCR, R12
esmHighInterrupt LDMFD R13!, {R12}
esmHighInterrupt VMSR FPEXC, R12
esmHighInterrupt LDMFD R13!, {R0, R1, R2, R3, R12, R14}
esmHighInterrupt SUBS PC, R14, #4
