Trigger EPI read on interrupt pin

Hi there,

I am using the Tiva C Series Connection Launchpad EK-TM4C1294XL. I have connected the first 10 Bits of the EPI-Port to the Omnivision OV5642 camera module. This module has an PCLK as output which clocks the 10 Bit parallel data out to the EPI. Is it possible to trigger a read on each PCLK pulse which then is written to an other memory location? The EPI mode is set to GPIO.

Here are the files so far for the EPI module:

EPI.h

/*
 * EPI.h
 *
 *  Created on: 27.05.2015
 *      Author: nicolas
 */

#ifndef EPI_H_
#define EPI_H_

#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>

#include "driverlib/epi.h"
#include "driverlib/sysctl.h"
#include "inc/hw_memmap.h"
#include "driverlib/gpio.h"
#include "driverlib/pin_map.h"
#include "inc/hw_epi.h"
#include "inc/hw_types.h"
#include "driverlib/rom.h"
#include "driverlib/rom_map.h"

class EPI {
	private:
		struct GPIOPin_t {
			uint32_t gpioBase;
			uint8_t pin;
			uint32_t altPin;
		};

		static uint32_t GPIOPeriph[];
		static GPIOPin_t GPIOPin[];

		static const uint32_t EPI_PORT = 0xA0000000;

		uint8_t bits;
		uint32_t bitMask;

	public:
		EPI(uint8_t bits) : bits(bits) {

			if (bits >= 32) {
				bits = 32;
				bitMask = 0xffffffff;
			} else {
				bitMask = (1 << bits) - 1;
			}

			for (uint8_t i = 0; i < 10; i++) {
				ROM_SysCtlPeripheralEnable(GPIOPeriph[i]);
				while (!(ROM_SysCtlPeripheralReady(GPIOPeriph[i])));
			}

			// Aktiviere EPI-Peripherie
			ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
			while (!(ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_EPI0)));

			for (uint8_t i = 0; i < bits; i++) {
				MAP_GPIOPinConfigure(GPIOPin[i].altPin);
				GPIODirModeSet(GPIOPin[i].gpioBase, GPIOPin[i].pin, GPIO_DIR_MODE_IN);
				GPIOPinTypeEPI(GPIOPin[i].gpioBase, GPIOPin[i].pin);
			}

			EPIModeSet(EPI0_BASE, EPI_MODE_GENERAL);

			EPIDividerSet(EPI0_BASE, 1);

			// EPI_GPMODE_CLKPIN is neccessary
			EPIConfigGPModeSet(EPI0_BASE, EPI_GPMODE_CLKPIN | EPI_GPMODE_ASIZE_NONE | EPI_GPMODE_DSIZE_16, 0, 0);

			//Address map to 0xA000.0000
			EPIAddressMapSet(EPI0_BASE, EPI_ADDR_PER_BASE_A | EPI_ADDR_PER_BASE_NONE);
		}

		~EPI() {
			ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_EPI0);
		}

		uint32_t inline read() {
			return HWREG(EPI_PORT) & bitMask;
		}

		void inline write(uint32_t value) {
			HWREG(EPI_PORT) = value & bitMask;
		}
};

#endif /* EPI_H_ */

EPI.cpp

/*
 * EPI.cpp
 *
 *  Created on: 27.05.2015
 *      Author: nicolas
 */

#include <components/EPI.h>

uint32_t EPI::GPIOPeriph[] = {
		SYSCTL_PERIPH_GPIOA,
		SYSCTL_PERIPH_GPIOB,
		SYSCTL_PERIPH_GPIOC,
		SYSCTL_PERIPH_GPIOG,
		SYSCTL_PERIPH_GPIOH,
		SYSCTL_PERIPH_GPIOK,
		SYSCTL_PERIPH_GPIOL,
		SYSCTL_PERIPH_GPIOM,
		SYSCTL_PERIPH_GPION,
		SYSCTL_PERIPH_GPIOQ
};

EPI::GPIOPin_t EPI::GPIOPin[] = {
		{ GPIO_PORTH_BASE, GPIO_PIN_0, GPIO_PH0_EPI0S0 },  /*  0 */
		{ GPIO_PORTH_BASE, GPIO_PIN_1, GPIO_PH1_EPI0S1 },  /*  1 */
		{ GPIO_PORTH_BASE, GPIO_PIN_2, GPIO_PH2_EPI0S2 },  /*  2 */
		{ GPIO_PORTH_BASE, GPIO_PIN_3, GPIO_PH3_EPI0S3 },  /*  3 */
		{ GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PC7_EPI0S4 },  /*  4 */
		{ GPIO_PORTC_BASE, GPIO_PIN_6, GPIO_PC6_EPI0S5 },  /*  5 */
		{ GPIO_PORTC_BASE, GPIO_PIN_5, GPIO_PC5_EPI0S6 },  /*  6 */
		{ GPIO_PORTC_BASE, GPIO_PIN_4, GPIO_PC4_EPI0S7 },  /*  7 */
		{ GPIO_PORTA_BASE, GPIO_PIN_6, GPIO_PA6_EPI0S8 },  /*  8 */
		{ GPIO_PORTA_BASE, GPIO_PIN_7, GPIO_PA7_EPI0S9 },  /*  9 */
		{ GPIO_PORTG_BASE, GPIO_PIN_1, GPIO_PG1_EPI0S10 }, /* 10 */
		{ GPIO_PORTG_BASE, GPIO_PIN_0, GPIO_PG0_EPI0S11 }, /* 11 */
		{ GPIO_PORTM_BASE, GPIO_PIN_3, GPIO_PM3_EPI0S12 }, /* 12 */
		{ GPIO_PORTM_BASE, GPIO_PIN_2, GPIO_PM2_EPI0S13 }, /* 13 */
		{ GPIO_PORTM_BASE, GPIO_PIN_1, GPIO_PM1_EPI0S14 }, /* 14 */
		{ GPIO_PORTM_BASE, GPIO_PIN_0, GPIO_PM0_EPI0S15 }, /* 15 */
		{ GPIO_PORTL_BASE, GPIO_PIN_0, GPIO_PL0_EPI0S16 }, /* 16 */
		{ GPIO_PORTL_BASE, GPIO_PIN_1, GPIO_PL1_EPI0S17 }, /* 17 */
		{ GPIO_PORTL_BASE, GPIO_PIN_2, GPIO_PL2_EPI0S18 }, /* 18 */
		{ GPIO_PORTL_BASE, GPIO_PIN_3, GPIO_PL3_EPI0S19 }, /* 19 */
		{ GPIO_PORTQ_BASE, GPIO_PIN_0, GPIO_PQ0_EPI0S20 }, /* 20 */
		{ GPIO_PORTQ_BASE, GPIO_PIN_1, GPIO_PQ1_EPI0S21 }, /* 21 */
		{ GPIO_PORTQ_BASE, GPIO_PIN_2, GPIO_PQ2_EPI0S22 }, /* 22 */
		{ GPIO_PORTQ_BASE, GPIO_PIN_3, GPIO_PQ3_EPI0S23 }, /* 23 */
		{ GPIO_PORTK_BASE, GPIO_PIN_7, GPIO_PK7_EPI0S24 }, /* 24 */
		{ GPIO_PORTK_BASE, GPIO_PIN_6, GPIO_PK6_EPI0S25 }, /* 25 */
		{ GPIO_PORTL_BASE, GPIO_PIN_4, GPIO_PL4_EPI0S26 }, /* 26 */
		{ GPIO_PORTB_BASE, GPIO_PIN_2, GPIO_PB2_EPI0S27 }, /* 27 */
		{ GPIO_PORTB_BASE, GPIO_PIN_3, GPIO_PB3_EPI0S28 }, /* 28 */
		{ GPIO_PORTN_BASE, GPIO_PIN_2, GPIO_PN2_EPI0S29 }, /* 29 */
		{ GPIO_PORTN_BASE, GPIO_PIN_3, GPIO_PN3_EPI0S30 }, /* 30 */
		{ GPIO_PORTK_BASE, GPIO_PIN_5, GPIO_PK5_EPI0S31 }, /* 31 */
		{ GPIO_PORTK_BASE, GPIO_PIN_4, GPIO_PK4_EPI0S32 }, /* 32 */
		{ GPIO_PORTL_BASE, GPIO_PIN_5, GPIO_PL5_EPI0S33 }, /* 33 */
		{ GPIO_PORTN_BASE, GPIO_PIN_4, GPIO_PN4_EPI0S34 }  /* 34 */
};