How to generate the two timer interrputs(timer 0 for 10 msec & timer1 for 20 msec)

One can use SysTick instead, which I find easier. Set the SysTick interrupt to fire at a an interval of 1 msec, then just simply count it 10 and 20 times to get 10msec and 20msec.

For example, if your microcontrollers clocking frequency is 120MHz, set the SysTick to wrap at 1200, which means it will enter the SysTick ISR every 0.01msec and make an interrupt routine to increment a value each time it does this. Then in your main piece of code, once this value has hit 1000 (10 msec / 0.01 msec) you have reached 10 msec.

SysTick config

void
InitSysTick(void)
{
/*	100,000 times per second it will call the interrupt.*/
	SysTickPeriodSet(1200);

	IntMasterEnable();

	SysTickIntEnable();

	SysTickEnable();
}

SysTick ISR

void
SysTickIntHandler(void)
{
/*	100,000 times per second.*/
	ui32SysTickCount++;
}

To get 10msec.

if((ui32SysTickCount - ui32SysTickCount10msec) >= 1000)
{
    		ui32SysTickCount10msec = ui32SysTickCount;
    		
    		//Execute code here.
    		
}

Hello James

Good from SW time keeping. But this will delay any HW pin changes. I suspect the reason of 10ms-20ms timing of the poster is more related to some kind of signal generation or sampling.

Regards
Amit

Hello Amit,

I was unaware of this limitation. Does using the Timer module prevent this from happening?

Hello James,

The timers are not just counters. They can be used to generate output signals as well. These output signals are driven when the condition to it matches. So consider the situation that a SysTick timer expires and generates an interrupt. The CPU would take X number of clocks before it reaches the condition to toggle a pin. Thus a delay of X clock gets introduced. Now if a NMI fires then the SysTick interrupt processing is held back by another Y clock cycles. This can thus cause the output pin toggle to be in the range of X to X+Y clock cycles.

Regards
Amit

Also the amount of delay will depend on the number of SW timers checked and so may get large and vary. There are ways to reduce the variation but they usually result in a larger fixed delay.

In addition a fast Systick adds overhead to everything, effectively slowing down the clock. IE if the Systick takes 1% of the processing time at a 1mS tick, it will take 10% when executed at 0.1mS. As a result it often makes sense to have the fastest timers be dedicated in order to reduce the overhead, especially in a processor with such a rich selection of timers as the TIVA.

Robert