Controller Datasheet or TivaDriver Library Incorrect.

Hello Amit,

I am using a direct wired cable (no crossover), and on the AM3352 we are using an external PHY.  I am still investigating to try to figure out what is going on, and right now I am thinking that the problem is likely on the AM3352 side.  I need to investigate what the Linux tool is doing regarding how it is determining the connection details. I am wondering if there is a problem with how it is handling reconnecting when a link has been lost. I am also thinking it is not reporting the correct information.

In one test that I performed the Linux tool was reporting that the Tiva was advertising it only supported 100BaseT Half duplex (with no auto negotiation enabled), and it was reporting that the AM3352 side was advertising it only supported 100BaseT full duplex. This is with the Tiva forced to 100BaseT Full duplex.  The tool also reported that the connection was established at 10BaseT.  I don't see how that is possible so I am thinking that the Linux tool is reporting incorrectly. I will investigate further and let you know what I find out!

Thanks for your help,

Cam

Hello Amit,

This is the scope trace I grabbed when I have the AM3352 side set with Auto negotiation enabled but with the only supported option set to 100BaseT Full Duplex. I have the Tiva side set to 100BaseT Full Duplex with no Auto negotiation. I am not sure what to make of this, can you tell me what is going on here?  I am also confused by the voltage levels I am seeing on the signals.

In this trace I had reset the Tiva to break the link, and then waited for the link to re-establish.  Channel 1 is Rx-, Channel 2 is Rx+, Channel 3 is Tx+ and Channel 4 is Tx-. Here is a table with the voltage levels:

Scope Settings:

ANALOG
Ch 1 Scale 2.00V/, Pos -5.92600V, Coup AC, BW Limit Off, Inv Off, Imp 1M Ohm
Probe 10.000000 : 1, Skew 0.0s
Ch 2 Scale 2.00V/, Pos -1.85000V, Coup AC, BW Limit Off, Inv Off, Imp 1M Ohm
Probe 10.000000 : 1, Skew 0.0s
Ch 3 Scale 2.00V/, Pos 2.02500V, Coup AC, BW Limit Off, Inv Off, Imp 1M Ohm
Probe 10.000000 : 1, Skew 0.0s
Ch 4 Scale 2.00V/, Pos 5.90000V, Coup AC, BW Limit Off, Inv Off, Imp 1M Ohm
Probe 10.000000 : 1, Skew 0.0s

TRIGGER
Sweep Mode Auto, Coup DC, Noise Rej Off, HF Rej Off, Holdoff 40.0ns
Mode Edge, Source Ch 1, Slope Rising, Level 150.00mV

HORIZONTAL
Mode Normal, Ref Center, Main Scale 2.000s/, Main Delay 1.399900000ms

ACQUISITION
Mode Normal, Realtime On, Vectors On, Persistence Off

Can you tell me what is going on here?  At the end of this exchange a link is established, but it is reporting that the link is 10BaseT and half duplex, even though neither side is configured to support 10BaseT.

Thanks!

Cam

We are using the Tivaware libraries for the initialization, and are calling the functions from our own wrapper.  I did have to create my own macros to pass the the EMACPHYConfigSet() function for the speed/duplexity settings. My definitions are as follows:

#define PERSONAL_EMAC_PHY_FORCE_10B_T_HALF_DUPLEX    0x00000000 //0b0000

#define PERSONAL_EMAC_PHY_FORCE_10B_T_FULL_DUPLEX    0x00000002 //0b0010

#define PERSONAL_EMAC_PHY_FORCE_100B_T_HALF_DUPLEX   0x00000004 //0b0100

#define PERSONAL_EMAC_PHY_FORCE_100B_T_FULL_DUPLEX   0x00000006 //0b0110

#define PERSONAL_EMAC_PHY_AN_10B_T_HALF_FULL_DUPLEX       0x00000008 //0b1000

#define PERSONAL_EMAC_PHY_AN_100B_T_HALF_FULL_DUPLEX       0x0000000A //0b1010

#define PERSONAL_EMAC_PHY_AN_10B_T_100B_T_HALF_DUPLEX      0x0000000C //0b1100

#define PERSONAL_EMAC_PHY_AN_10B_T_HALF_FULL_100B_T_HALF_FULL_DUPLEX      0x0000000E //0b1110

I am configuring the ethernet with this call.

EMACPHYConfigSet(EMAC0_BASE,
(EMAC_PHY_TYPE_INTERNAL | EMAC_PHY_INT_MDIX_EN |
PERSONAL_EMAC_PHY_FORCE_100B_T_FULL_DUPLEX |
EMAC_PHY_INT_ROBUST_MDIX ));

Hi Cam,

Just wondering have you configured (lwipopt.h) for 100MB auto negotiate, assumes the TCP stack also invokes (tiva-tm4c129.c).

BTW: The PHY link state interrupt was not enabled in tiva abstraction code. Our 5 port switch indicates via LED when 100MB handshake. Sometimes switch ports my not be configured to auto detect mode and have a fixed rate thus assuming the client will follow the port master.

Your low level device code looks something like that below?

EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1, (EPHY_MISR1_LINKSTATEN |    //REG88:EPHY_MISR1_LINKSTATEN
             EPHY_MISR1_SPEEDEN | EPHY_MISR1_DUPLEXMEN | EPHY_MISR1_ANCEN));

  /* Tell the PHY to start an auto-negotiation cycle. */
  EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMCR, (EPHY_BMCR_ANEN |
               EPHY_BMCR_RESTARTAN));

Cam Shaw said:

The Datasheet says that a setting of 0x01 will set it to 100Base-TX, Half/Full Duplex when ANEN is set to 0x01.

The Tiva Driver Library says the following:

EMAC_PHY_AN_10B_T_FULL_DUPLEX enables auto-negotiation and advertises
10Base-T half or full duplex modes (sets the default value of PHY register MR9 bits [13:11]
to 3b101).

The tests were performed with the remote Ethernet link phy LAN8710A, connected to an AM3352. The LAN8710A was set to auto-negotiate advertising 100M Full Duplex, 100M Half Duplex, 10M Full Duplex and 10M Half Duplex.

To investigate what the TM4C1294 internal Ethernet phy was being set to the following code was used to report register settings in a TI-RTOS program after a TCP connection had been established:

    uint32_t emac_pc;
    uint16_t phy_ana;
    uint16_t phy_anlpa;

    /* Debug the Ethernet phy Autonegotation.
     * The assumption is that once get a TCP connection auto-negotiation must have completed. */
    emac_pc = HWREG (EMAC0_BASE + EMAC_O_PC);
    System_printf ("EMAC_0_PC=0x%x : Auto Negotiation Enable=%u Auto Negotiation Mode=%u\n",
    		emac_pc, (emac_pc & EMAC_PC_ANEN) >> 3, (emac_pc & EMAC_PC_ANMODE_M) >> 1);
    System_flush();

    phy_ana = EMACPHYRead (EMAC0_BASE, PHY_PHYS_ADDR, EPHY_ANA);
    System_printf ("EPHY_ANA=0x%x : %s%s%s%s%s\n", phy_ana,
    		(phy_ana & EPHY_ANA_100BT4) ? "  100Base-T4" : "",
    		(phy_ana & EPHY_ANA_100BTXFD) ? "  100Base-TX Full Duplex" : "",
    		(phy_ana & EPHY_ANA_100BTX) ? "  100Base-TX" : "",
    		(phy_ana & EPHY_ANA_10BTFD) ? "  10Base-T Full Duplex" : "",
    		(phy_ana & EPHY_ANA_10BT) ? "  10Base-T" : "");
    System_flush();

    phy_anlpa = EMACPHYRead (EMAC0_BASE, PHY_PHYS_ADDR, EPHY_ANLPA);
    System_printf ("EPHY_ANLPA=0x%x : %s%s%s%s%s\n", phy_anlpa,
    		(phy_anlpa & EPHY_ANLPA_100BT4) ? "  100Base-T4" : "",
    		(phy_anlpa & EPHY_ANLPA_100BTXFD) ? "  100Base-TX Full Duplex" : "",
    		(phy_anlpa & EPHY_ANLPA_100BTX) ? "  100Base-TX" : "",
    		(phy_anlpa & EPHY_ANLPA_10BTFD) ? "  10Base-T Full Duplex" : "",
    		(phy_anlpa & EPHY_ANLPA_10BT) ? "  10Base-T" : "");
    System_flush();

Where:

- The EMAC_0_PC value is the contents of the Ethernet MAC Peripheral Configuration Register

- The EPHY_ANA is the contents of the internal Ethernet PHY Auto-Negotiation Advertisement - MR4 Register

- The EPHY_ANLPA is the contents of the internal Ethernet PHY Auto-Negotiation Link Partner Ability - MR5

The test results are:

1) Calling EMACPHYConfigSet(EMAC0_BASE, EMAC_PHY_TYPE_INTERNAL | EMAC_PHY_INT_MDIX_EN | EMAC_PHY_AN_10B_T_HALF_DUPLEX) results in the link auto-negotiating to 10M Full Duplex, where as the expected link speed was 10M Half Duplex.

Debug output:

EMAC_0_PC=0x408 : Auto Negotiation Enable=1 Auto Negotiation Mode=0
EPHY_ANA=0x61 : 10Base-T Full Duplex 10Base-T
EPHY_ANLPA=0x41e1 : 100Base-TX Full Duplex 100Base-TX 10Base-T Full Duplex 10Base-T

2) Calling EMACPHYConfigSet(EMAC_PHY_TYPE_INTERNAL | EMAC_PHY_INT_MDIX_EN | EMAC_PHY_AN_10B_T_FULL_DUPLEX) results in the link auto-negotiating to 100M Full Duplex, where as the expected link speed was 10M Full Duplex.

Debug output:

EMAC_0_PC=0x40a : Auto Negotiation Enable=1 Auto Negotiation Mode=1
EPHY_ANA=0x181 : 100Base-TX Full Duplex 100Base-TX
EPHY_ANLPA=0x41e1 : 100Base-TX Full Duplex 100Base-TX 10Base-T Full Duplex 10Base-T

3) Calling EMACPHYConfigSet(EMAC_PHY_TYPE_INTERNAL | EMAC_PHY_INT_MDIX_EN | EMAC_PHY_AN_100B_T_HALF_DUPLEX) results in the link auto-negotiating to 100M Half Duplex which is the expected result.

Debug output:

EMAC_0_PC=0x40c : Auto Negotiation Enable=1 Auto Negotiation Mode=2
EPHY_ANA=0xa1 : 100Base-TX 10Base-T
EPHY_ANLPA=0x41e1 : 100Base-TX Full Duplex 100Base-TX 10Base-T Full Duplex 10Base-T

4) Calling EMACPHYConfigSet(EMAC_PHY_TYPE_INTERNAL | EMAC_PHY_INT_MDIX_EN | EMAC_PHY_AN_100B_T_FULL_DUPLEX) results in the link auto-negotiating to 100M Full Duplex which is the expected result.

Debug Output:

EMAC_0_PC=0x40e : Auto Negotiation Enable=1 Auto Negotiation Mode=3
EPHY_ANA=0x1e1 : 100Base-TX Full Duplex 100Base-TX 10Base-T Full Duplex 10Base-T
EPHY_ANLPA=0x41e1 : 100Base-TX Full Duplex 100Base-TX 10Base-T Full Duplex 10Base-T

The conclusion is that the EMACPHYConfigSet call using EMAC_PHY_AN_10B_T_HALF_DUPLEX, EMAC_PHY_AN_10B_T_FULL_DUPLEX, EMAC_PHY_AN_100B_T_HALF_DUPLEX or EMAC_PHY_AN_100B_T_FULL_DUPLEX is enabling auto-negotiation in the Ethernet MAC Peripheral Configuration Register with the Auto Negotiation Mode set to different values. However, the advertised modes don't match the TivaWare descriptions for EMAC_PHY_AN_100B_T_HALF_DUPLEX or EMAC_PHY_AN_100B_T_FULL_DUPLEX:

Will try a modification to EMACPHYConfigSet to write to the internal Ethernet PHY Auto-Negotiation Advertisement - MR4 Register to set the correct values for EMAC_PHY_AN_100B_T_HALF_DUPLEX or EMAC_PHY_AN_100B_T_FULL_DUPLEX.

BP101 said:

I noticed neither his code or your debug show a calling to the EMACInit anytime after calling EMACConfigSet for indirect update writing the link speed into the internal PHY.

    EMACPHYConfigSet(EMAC0_BASE, EMAC_PHY_CONFIG);

    BIOS_getCpuFreq(&freq);
    EMACInit(EMAC0_BASE, freq.lo,
             EMAC_BCONFIG_MIXED_BURST | EMAC_BCONFIG_PRIORITY_FIXED,
             4, 4, 0);

    /* Set MAC configuration options. */
    EMACConfigSet(EMAC0_BASE, (EMAC_CONFIG_FULL_DUPLEX |
                               //EMAC_CONFIG_CHECKSUM_OFFLOAD |
                               EMAC_CONFIG_7BYTE_PREAMBLE |
                               EMAC_CONFIG_IF_GAP_96BITS |
                               EMAC_CONFIG_USE_MACADDR0 |
                               EMAC_CONFIG_SA_FROM_DESCRIPTOR |
                               EMAC_CONFIG_BO_LIMIT_1024),
                  (EMAC_MODE_RX_STORE_FORWARD |
                   EMAC_MODE_TX_STORE_FORWARD |
                   EMAC_MODE_TX_THRESHOLD_64_BYTES |
                   EMAC_MODE_RX_THRESHOLD_64_BYTES), 0);

In TivaWare 2.1.1.71 the EMACPHYConfigSet function when called with EMAC_PHY_AN_10B_T_HALF_DUPLEX, EMAC_PHY_AN_10B_T_FULL_DUPLEX, EMAC_PHY_AN_100B_T_HALF_DUPLEX or EMAC_PHY_AN_100B_T_FULL_DUPLEX for the internal Phy writes to the Ethernet MAC Peripheral Configuration Register with the ANEN bit set to enable auto-negotiation and with different values of the ANMODE field. The AMMODE field setting is use to set the advertised capabilities in the internal Ethernet PHY Auto-Negotiation Link Partner Ability - MR5 register. Following a write to the ANMODE field the advertised capabilities in the internal Ethernet PHY Auto-Negotiation Link Partner Ability - MR5 register match those given in the device datasheet, but don't match the documentation for the TivaWare EMAC_PHY_AN_10B_T_HALF_DUPLEX, EMAC_PHY_AN_10B_T_FULL_DUPLEX or EMAC_PHY_AN_100B_T_HALF_DUPLEX  definitions (EMAC_PHY_AN_100B_T_FULL_DUPLEX is OK).

The following modified version of the TivaWare EMACPHYConfigSet function was used to explicitly set the advertised capabilities in the internal Ethernet PHY Auto-Negotiation Link Partner Ability - MR5 register to values which match the TivaWare EMAC_PHY_AN_10B_T_HALF_DUPLEX, EMAC_PHY_AN_10B_T_FULL_DUPLEX, EMAC_PHY_AN_100B_T_HALF_DUPLEX or EMAC_PHY_AN_100B_T_FULL_DUPLEX definitions:

void
EMACPHYConfigSet(uint32_t ui32Base, uint32_t ui32Config)
{
    uint16_t phy_ana;
    uint16_t expected_advertisment;
    uint16_t actual_advertisment;
    const uint16_t advertisment_mask = EPHY_ANA_100BT4 | EPHY_ANA_100BTXFD | EPHY_ANA_100BTX | EPHY_ANA_10BTFD | EPHY_ANA_10BT;
    const uint8_t internal_phy_address = 0;

    if((ui32Config & EMAC_PHY_TYPE_MASK) == EMAC_PHY_TYPE_INTERNAL)
    {
    	/* Prevent the internal Phy from transmitting engery until have determined the advertised
    	 * capability has been set correctly. */
    	ui32Config |= EMAC_PC_PHYHOLD;
    }

    //
    // Write the Ethernet PHY configuration to the peripheral configuration
    // register.
    //
    HWREG(ui32Base + EMAC_O_PC) = ui32Config;

    //
    // If using the internal PHY, reset it to ensure that new configuration is
    // latched there.
    //
    if((ui32Config & EMAC_PHY_TYPE_MASK) == EMAC_PHY_TYPE_INTERNAL)
    {
        SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0);
        while(!SysCtlPeripheralReady(SYSCTL_PERIPH_EPHY0))
        {
            //
            // Wait for the PHY reset to complete.
            //
        }

        //
        // Delay a bit longer to ensure that the PHY reset has completed.
        //
        SysCtlDelay(10000);

        /* Determine which Ethernet phy auto-negotiation capabilities are expected to be
         * advertised, based upon the requested parameters. */
        switch (ui32Config & (EMAC_PC_ANEN | EMAC_PC_ANMODE_M))
        {
        case EMAC_PHY_AN_10B_T_HALF_DUPLEX:
        	expected_advertisment = EPHY_ANA_10BT;
        	break;

        case EMAC_PHY_AN_10B_T_FULL_DUPLEX:
        	expected_advertisment = EPHY_ANA_10BTFD | EPHY_ANA_10BT;
        	break;

        case EMAC_PHY_AN_100B_T_HALF_DUPLEX:
        	expected_advertisment = EPHY_ANA_100BTX | EPHY_ANA_10BTFD | EPHY_ANA_10BT;
        	break;

        case EMAC_PHY_AN_100B_T_FULL_DUPLEX:
        	expected_advertisment = EPHY_ANA_100BTXFD | EPHY_ANA_100BTX | EPHY_ANA_10BTFD | EPHY_ANA_10BT;
        	break;

        default:
        	expected_advertisment = 0;
        	break;
        }

        if (expected_advertisment != 0)
        {
            /* Read the actual auto-negotiation capabilities which are being advertised by the internal Phy
             * following the above write to the EMAC_O_PC register. */
            phy_ana = EMACPHYRead (ui32Base, internal_phy_address, EPHY_ANA);
            actual_advertisment = phy_ana & advertisment_mask;

            if (actual_advertisment != expected_advertisment)
            {
            	/* The internal Phy isn't advertising the expected auto-negotiation capabilities,
            	 * so change to advertise the expected auto-negotation capabilities */
            	phy_ana &= ~advertisment_mask;
            	phy_ana |= expected_advertisment;
            	EMACPHYWrite (ui32Base, internal_phy_address, EPHY_ANA, expected_advertisment);
            }
        }

        /* Allow the internal Phy to complete it's internal reset sequence */
        EMACPHYWrite (ui32Base, internal_phy_address, EPHY_CFG1,
        		      EMACPHYRead (ui32Base, internal_phy_address, EPHY_CFG1) | EPHY_CFG1_DONE);
    }

    //
    // If using an external RMII PHY, we must set 2 bits in the Ethernet MAC
    // Clock Configuration Register.
    //
    if((ui32Config & EMAC_PHY_TYPE_MASK) == EMAC_PHY_TYPE_EXTERNAL_RMII)
    {
        //
        // Select and enable the external clock from the RMII PHY.
        //
        HWREG(EMAC0_BASE + EMAC_O_CC) |= EMAC_CC_CLKEN;
    }
    else
    {
        //
        // Disable the external clock.
        //
        HWREG(EMAC0_BASE + EMAC_O_CC) &= ~EMAC_CC_CLKEN;
    }

    //
    // Reset the MAC regardless of whether the PHY connection changed or not.
    //
    EMACReset(EMAC0_BASE);

    SysCtlDelay(1000);
}

The results of testing the modified EMACPHYConfigSet function showed the TM4C1294NCPDT internal Ethernet Phy then auto-negotiated to the expected link speed and duplex:

1) Calling EMACPHYConfigSet(EMAC0_BASE, EMAC_PHY_TYPE_INTERNAL | EMAC_PHY_INT_MDIX_EN | EMAC_PHY_AN_10B_T_HALF_DUPLEX) results in the link auto-negotiating to 10M Half Duplex.

Debug output:

EMAC_0_PC=0x409 : Auto Negotiation Enable=1 Auto Negotiation Mode=0
EPHY_ANA=0x20 : 10Base-T
EPHY_ANLPA=0x41e1 : 100Base-TX Full Duplex 100Base-TX 10Base-T Full Duplex 10Base-T

2) Calling EMACPHYConfigSet(EMAC_PHY_TYPE_INTERNAL | EMAC_PHY_INT_MDIX_EN | EMAC_PHY_AN_10B_T_FULL_DUPLEX) results in the link auto-negotiating to 10M Full Duplex.

Debug output:

EMAC_0_PC=0x40b : Auto Negotiation Enable=1 Auto Negotiation Mode=1
EPHY_ANA=0x60 : 10Base-T Full Duplex 10Base-T
EPHY_ANLPA=0x41e1 : 100Base-TX Full Duplex 100Base-TX 10Base-T Full Duplex 10Base-T

3) Calling EMACPHYConfigSet(EMAC_PHY_TYPE_INTERNAL | EMAC_PHY_INT_MDIX_EN | EMAC_PHY_AN_100B_T_HALF_DUPLEX) results in the link auto-negotiating to 100M Half Duplex.

Debug output:

EMAC_0_PC=0x40d : Auto Negotiation Enable=1 Auto Negotiation Mode=2
EPHY_ANA=0xe0 : 100Base-TX 10Base-T Full Duplex 10Base-T
EPHY_ANLPA=0x41e1 : 100Base-TX Full Duplex 100Base-TX 10Base-T Full Duplex 10Base-T

4)  Calling EMACPHYConfigSet(EMAC_PHY_TYPE_INTERNAL | EMAC_PHY_INT_MDIX_EN | EMAC_PHY_AN_100B_T_FULL_DUPLEX) results in the link auto-negotiating to 100M Full Duplex.

Debug output:

EMAC_0_PC=0x40f : Auto Negotiation Enable=1 Auto Negotiation Mode=3
EPHY_ANA=0x1e1 : 100Base-TX Full Duplex 100Base-TX 10Base-T Full Duplex 10Base-T
EPHY_ANLPA=0x41e1 : 100Base-TX Full Duplex 100Base-TX 10Base-T Full Duplex 10Base-T

In summary, believe have identified a problem in how the TivaWare EMACPHYConfigSet handles the EMAC_PHY_AN_10B_T_HALF_DUPLEX, EMAC_PHY_AN_10B_T_FULL_DUPLEX or EMAC_PHY_AN_100B_T_HALF_DUPLEX definitions when the internal Ethernet Phy is used.

Hi Chester,

>In summary, believe have identified a problem in how the TivaWare EMACPHYConfigSet handles the EMAC_PHY_AN_10B_T_HALF_DUPLEX,

Was wondering when you were going to get that last point. :) Yet my code sets also the link speed albeit NO_SYS=1. Wonder if that has something to do with why the PHY is so dang obstinate. My take on registers text, store and forward thresholds have no effect unless RSF bit 21, 25 are each clear. Had some issues with default TI configuration causing random exceptions.

    MAP_EMACConfigSet(EMAC0_BASE, (EMAC_CONFIG_FULL_DUPLEX | EMAC_CONFIG_100MBPS |
                                   EMAC_CONFIG_CHECKSUM_OFFLOAD |
                                   EMAC_CONFIG_7BYTE_PREAMBLE |
                                   EMAC_CONFIG_IF_GAP_96BITS |
                                   EMAC_CONFIG_USE_MACADDR0 |
                                   EMAC_CONFIG_SA_FROM_DESCRIPTOR |
                                   EMAC_CONFIG_BO_LIMIT_1024),
				/* Configure REG-58:0xC18 (EMACDMAOPMODE) DMA engines mode flags
				 * operate first frame, store and forward,  max frame size  */
			      (EMAC_MODE_RX_STORE_FORWARD | //set RSF[25], (Reset) clears
				EMAC_MODE_TX_STORE_FORWARD | //set TSF[21], (Reset) clears
				EMAC_DMAOPMODE_DGF), 2048);  // TTC/RTC Ignored (TX/RX(SF)[21,25] are set