RM48 startup DMA RAM PBIST

Ryan Smoots

Other Parts Discussed in Thread: RM48L952, HALCOGEN

I used HALCoGen to generate startup code in HL_sys_startup.c for the RM48L952 including a memory built in self test on DMA RAM as follows:

    pbistRun(  (uint32)0x00000000U    /* EMAC RAM */
             | (uint32)0x00000000U    /* USB RAM */
             | (uint32)0x00000800U    /* DMA RAM */
             | (uint32)0x00000000U    /* VIM RAM */
             | (uint32)0x00000000U    /* MIBSPI1 RAM */
             | (uint32)0x00000000U    /* MIBSPI3 RAM */
             | (uint32)0x00000000U    /* MIBSPI5 RAM */
             | (uint32)0x00000000U    /* CAN1 RAM */
             | (uint32)0x00000000U    /* CAN2 RAM */
             | (uint32)0x00000000U    /* CAN3 RAM */
             | (uint32)0x00000400U    /* ADC1 RAM */
             | (uint32)0x00000000U    /* ADC2 RAM */
             | (uint32)0x00000000U    /* HET1 RAM */
             | (uint32)0x00000000U    /* HET2 RAM */
             | (uint32)0x00000000U    /* HTU1 RAM */
             | (uint32)0x00000000U    /* HTU2 RAM */
             | (uint32)0x00000000U    /* RTP RAM */
             | (uint32)0x00000000U    /* FRAY RAM */
             ,(uint32) PBIST_March13N_DP);

Note that the only two RAMs which have the PBIST enabled are DMA and ADC1.

When the DMA RAM PBIST is run on startup the DMA does not work. When I disable the DMA RAM PBIST it works again.

Looking into the cause I found that the control packet in use (control packet 0) does not get populated when the DMA RAM PBIST is run. See the attached memory dumps for comparison. Note that 0xFFF80000 is the base address of control packet 0 and 0xFFFFF000 is the base address of the DMA control registers. Both data dumps were taken after running the application for approximately 1 minute.

DMA RAM PBIST disabled:

DMA RAM PBIST enabled:

Note that DMA control packet 0 is cleared. Why does the DMA RAM PBIST cause control packet 0 to fail?

Thanks,

Ryan

over 10 years ago

0 Chuck Davenport over 10 years ago

TI__Guru 59540 points

Hello Ryan,

Can you check the placement of the DMA configuration routines. They should be placed after the startup code is completed including PBIST because PBIST is a destructive test.

If you confirm that you have the right order of startup tests and DMA configuration, it would be helpful if you could post your project so we could have a look at it.

0 Ryan Smoots over 10 years ago in reply to Chuck Davenport

Intellectual 260 points

DMA is configured after the PBIST.

I can't just upload my project. However, I have uploaded the auto-generated HL_sys_startup.c which is essentially identical to the one I am using. Any other ideas?2235.HL_sys_startup.c

0 Chuck Davenport over 10 years ago in reply to Ryan Smoots

TI__Guru 59540 points

Hello Ryan,

I don't see anything wrong in your HL_sys_startup.c file. Can you send me your sys_main.c and your DMA drivers so I can see where and how you are initializing the DMA control registers?

0 Ryan Smoots over 10 years ago in reply to Chuck Davenport

Intellectual 260 points

Yes, here are the DMA driver files:

2860.HL_reg_dma.h

0777.HL_sys_dma.c

7585.HL_sys_dma.h

All of the DMA driver functions (except dmaBTCAInterrupt) are called from UART drivers which are called from main and/or RIO.

0 Chuck Davenport over 10 years ago in reply to Ryan Smoots

TI__Guru 59540 points

Hi Ryan,

What I am trying to look at is your code were you setup the DMA. i.e., where you enable DMA, setup the notifications, configure the control packet, etc. Do you call the dma enable function to enable the module? What you describe seems as though the module is in reset and not taking any writes to the DMA registers.

Also, there is an example and application note of an SCI-DMA implementation available now that might be beneficial to look at and compare with your implementation.

www.ti.com/.../spna213.pdf

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RM48 startup DMA RAM PBIST