I believe that the assembly code provided by HALCOGEN for FreeRTOS in os_portasm.{asm,s} is incorrect. In particular, while some SVC vectors clobber r0, the entry/exit code in vPortSWI does not save r0. Recall that r0 is not a banked register, and unlike ARMv7-M, it is not automatically stacked by the hardware on exception entry, either.
The TI compiler does not seem to be affected, since it does not seem to be saving anything in r0 (only v1) in the relevant code section. However, the GCC toolchain does use r0. When optimization is enabled, the HALCOGEN-provided port of FreeRTOS fails to run.