Problem on TM4C129x EPI "Dual Chip Select"

Hello Ay0689,

The 0x60000000 is on CS0 and 0xA0000000 is on CS1. The concerto device uses the same EPI as TM4C129x.

Can you share the full configuration of EPI registers for us to double check.

Regards
Amit

Hello Amit-san, 

ｔhank you for your quick response.

Our EPI settings are as follows,

EPICFG		0x400D_0000		0x0000_0013
EPIHB16CFG		0x400D_0010		0x0008_0054
EPIHB16CFG2		0x400D_0014		0x0300_0000
EPIADDRMAP		0x400D_001C		0x0000_00d9

The source-codes are as follows;

EPIConfigGPModeSet(EPI0_BASE, (EPI_GPMODE_CLKPIN), 0, 0);
EPIModeSet(EPI0_BASE, EPI_MODE_HB16);
EPIDividerSet(EPI0_BASE, 0);
EPIConfigHB16Set(EPI0_BASE, (EPI_HB16_MODE_ADMUX | EPI_HB16_WRWAIT_1 | EPI_HB16_RDWAIT_1 | EPI_HB16_WORD_ACCESS | EPI_HB16_BSEL | EPI_HB16_CSCFG_ALE_DUAL_CS | EPI_HB16_ALE_HIGH), 0);

EPIAddressMapSet(EPI0_BASE, (EPI_ADDR_PER_SIZE_256MB | EPI_ADDR_PER_BASE_A | EPI_ADDR_RAM_SIZE_16MB | EPI_ADDR_RAM_BASE_6));

Best regards,

ay0689

Hello Ay0689,

Yes, I can confirm that the table is not correct. The Address map is swapped.

Regards
Amit

Hello Amit-san,

I think that it is difficult for us to use "ALE with Dual CSn Configuration" for the sake of this CSn SWAP problem.

we are planning to use "ALE with Quad CSn Configration" in place of "ALE with Dual CSn Configuration" as THE WORKAROUND. 

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ALE with Quad CSn Configuration

EPI0S30 is ALE, EPI0S26 is CS0n and EPI0S27 is used as CS1n. EPI0S34 is used as CS2n and EPI0S33 is used as CS3n.

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Do you have any other solution as the Workaround?

Best regards,

ay0689

Hello Ay0689,

Isn't it easy to do it in the SW to change the address of access to the Chip Select?

Regards
Amit

Hi Amit,

I ran into the same problem and found this post.

How would you suggest this to be implemented in SW? The RAM adress (0x6000 or 0x8000) will always be lower as the Peripheral adress (0xA000 or 0xC000) thus RAM will always be on the lower CS (CS0n).  Then which of the EPI0S signals is CS0n and which is CS1n? The ROM user guide and Datasheet don't seem to agree on that.

Thanks for your help,

Best regards,

Frederic

Hello Frederic,

You are correct, the Chip Selects are swapped. Hence if the PCB has been laid out then the changed would be in the SW to swap the address as well to get the same function back.

Regards
Amit

Hi again Amit,

Ok thanks, the PCB has NOT yet been compeletly routed, therefore I am asking.
Would that be something that get fixed in the future or we can design "safely" with the swapped CS0n CS1n? What about Quad CS, are 0 and 1 still swapped?

And I guess that by the SW solution I just initialize my strucures pointing on the other addresse for example my Peripheral (FPGA) would be initialized at the RAM adress and vice-versa.

Thanks,

Frederic

Hello Frederic,

No, there is no plan to fix the same. In Quad CS the pins would not be swapped. A simple experiment can confirm that.

Regards
Amit