Access memory protect by MPU

Hello Jason

A fault cannot cause a CPU reset, unless there is a Watchdog running. So the question is that is the WatchDog on the device running?

Regards
Amit

Hi Amit:
Thank you for your reply!
On the device the watchdog is running actually. If I can't disable the watchdog, and don't want the MCU reset when the memory management fault occurs, is that possible? Can it be solved by register a handler to catch the fault?

Regards
Jason

Hello Jason,

When a bus fault occurs it jumps to the fault handler. One thing that can be done is to disable the WatchDog timer clock in the FaultISR, so that the CPU is available for inspection of the bus fault.

Regards
Amit

Hello Amit:
If I don't disable the WatchDog timer clock in the FaultISR, Can the fault handler catch the fault? We register a fault handler for the memory management fault, but the handler don't work when the fault occurs. The reason is the WatchDog timer clock in the FaultISR?

Hello Jason,

To better get the context, which TM4C device are you using and when you refer to a MMU fault can you please specify which fault register and corresponding bit?

Regards
Amit

MCU:TM4C123GH6PZ Microcontroller
Code for register handler:
#pragma DATA_SECTION(g_pfnVectors, ".intvecs")
void (* const g_pfnVectors[])(void) =
{
(void (*)(void))((unsigned long)&__STACK_TOP),
// The initial stack pointer
ResetISR, // The reset handler
NmiSR, // The NMI handler
FaultISR, // The hard fault handler
MPUFaultHandler, // The MPU fault handler
};

Is that enough?

Hello Jason,

Can you add the clock disable to the watchdog in the fault handler and then see if it still remains there?

Regards
Amit