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CCM-R4F in lockstep mode

user4176445
Prodigy 90 points
Other Parts Discussed in Thread: TMS570LS3137

HAL 04.04.00

Device:TMS570LS3137

IAR

 

In lock step mode, the compare bus output signals of both CPUs are compared.A difference in the CPU

compare bus outputs is indicated by signalling an error to the ESM which sets the error flag “CCM-R4F -compare”.

My question is：

In lock step mode,when there is a difference in the CPU compare bus outputs.In this time,the error flag “CCM-R4F -compare” in the ESM will be set. But, I don’t know what should I do at this addition.

How can I enter into the ESM high interrupt? Where can I find my ISR(interrupt service routine)? What should I do in my ISR?

If there is a difference in the CPU compare bus outputs in lock step mode, what will be in effect?

  • 0
    TI__Genius 11645 points
    Hi,

    CCM errors happen when there is a mis-match seen b/w both the CPU's running in lock-step mode.

    In an application, if CCM error is encountered due to a mismatch its fatal and hence this is connected to ESM module Group-2, which is high severity.

    Since its group-2 it generates an FIQ interrupt as well as toggles nERROR pin on the I/O to indicate there is something severe to the outside world.

    Since this does not generate an internal reset, user needs to handle outside using appropriate circuitry for resetting the device if you intend to.
  • 0 in reply to KARTHIKEYAN RAJAMANICKAM
    Prodigy 90 points
    Hi,
    Thank you for your answer.
    Next is my question:
    If there is a mis-match running in lock-step mode, then ESM group2 channel2 generates an FIQ interrupt.
    I want to know if the code will jump into the esmHighInterrupt(), then enter into esmGroup2Notification(uint32 channel).
    If yes, I want to know what should I do in the esmGroup2Notification(esmChannel2), for compare error ,if I must reset the device.
  • 0 in reply to user4176445
    TI__Genius 11645 points
    Hi,

    I'm assigning your thread to our safety team to respond with what exactly we recommend.

    Ideally since your CPU had already mal-functioned its not safe anymore to execute an ISR predictably, so you can use the nERROR event and control the external reset (TPS supports deciding when to generate a reset w.r.t nERROR which gives you time to do some clean-up if you want to).
  • 0 in reply to KARTHIKEYAN RAJAMANICKAM
    Prodigy 90 points
    Hi,
    Thank you for your reply.
    I get your idea. You mean if there is a compare error in CPU, the best solve program is reset, and it is hardware reset. Am I right?

    I have another question:
    I run C/OS-Ⅱ on my device.
    I don‘t choose CCM selftest, also don't choose ESM group 1 channel 31.
    without connect debugger.
    In my task, I set the force-error mode. the code can enter into ISR, also the nERROR pin state is right. But the code run the ISR finished, then the device restart.I don't know why?
  • 0 in reply to user4176445
    TI__Genius 11645 points
    Hi,

    There is no reset that's generated internal from the device, apart from generating the interrupt and toggling the nERROR I/O.

    If your nERROR I/O is connected to some of the external monitoring circuitry, that could be generating this reset. That's the only way you can see a reset on CCM error.