EPI Clock Absent on TM4C129XL

Joseph Curasi said:

...clock is referenced in the timing diagrams, but is mysteriously absent ...from the pin 

Surely Amit's post "nails" this - yet we must note that vital "set-up/config code" - key in resolution - also is, "mysteriously absent!"

Hello cb1,

Yes indeed. The full configuration is required as well.

Regards
Amit

Hi Amit,

Yes, I omitted the EPICLK configuration statements. Here is the complete setup:

// Enable the EPI peripheral
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);

//---------------------------------------------------------------
// GPIO PORTS USED FOR EPI
//---------------------------------------------------------------

ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOP);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);



// Address Data Bus (AD7:AD0)
ROM_GPIOPinConfigure(GPIO_PK0_EPI0S0); // AD0
GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_0);

ROM_GPIOPinConfigure(GPIO_PK1_EPI0S1);
GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_1);

ROM_GPIOPinConfigure(GPIO_PK2_EPI0S2);
GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_2);

ROM_GPIOPinConfigure(GPIO_PK3_EPI0S3);
GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_3);

ROM_GPIOPinConfigure(GPIO_PC7_EPI0S4);
GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_7);

ROM_GPIOPinConfigure(GPIO_PC6_EPI0S5);
GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_6);

ROM_GPIOPinConfigure(GPIO_PC5_EPI0S6);
GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_5);

ROM_GPIOPinConfigure(GPIO_PC4_EPI0S7); // AD7
GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_4);

// Control Signals
ROM_GPIOPinConfigure(GPIO_PP3_EPI0S30); // nALE
GPIOPinTypeEPI(GPIO_PORTP_BASE, GPIO_PIN_3);

ROM_GPIOPinConfigure(GPIO_PP2_EPI0S29); // nWR
GPIOPinTypeEPI(GPIO_PORTP_BASE, GPIO_PIN_2);

ROM_GPIOPinConfigure(GPIO_PB3_EPI0S28); // nOE
GPIOPinTypeEPI(GPIO_PORTB_BASE, GPIO_PIN_3);

ROM_GPIOPinConfigure(GPIO_PK5_EPI0S31); // EPICLK
GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_5);


// Address Bus (A20:A8)
ROM_GPIOPinConfigure(GPIO_PA6_EPI0S8); // A8
GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_6);

ROM_GPIOPinConfigure(GPIO_PA7_EPI0S9);
GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_7);

ROM_GPIOPinConfigure(GPIO_PG1_EPI0S10);
GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_1);

ROM_GPIOPinConfigure(GPIO_PG0_EPI0S11);
GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_0);

ROM_GPIOPinConfigure(GPIO_PM3_EPI0S12);
GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_3);

ROM_GPIOPinConfigure(GPIO_PM2_EPI0S13);
GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_2);

ROM_GPIOPinConfigure(GPIO_PM1_EPI0S14);
GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_1);

ROM_GPIOPinConfigure(GPIO_PM0_EPI0S15);
GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_0);

ROM_GPIOPinConfigure(GPIO_PL0_EPI0S16);
GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_0);

ROM_GPIOPinConfigure(GPIO_PL1_EPI0S17);
GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_1);

ROM_GPIOPinConfigure(GPIO_PL2_EPI0S18);
GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_2);

ROM_GPIOPinConfigure(GPIO_PL3_EPI0S19);
GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_3);

ROM_GPIOPinConfigure(GPIO_PQ0_EPI0S20);
GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_0); // A20





//---------------------------------------------------------------
// EPI Setup
//---------------------------------------------------------------

// Set the EPI divider.
ROM_EPIDividerSet(EPI0_BASE, 1); // Set to 1 (Do not set to 0)

// Select EPI Host Bus 8-bit mode.
ROM_EPIModeSet(EPI0_BASE, EPI_MODE_HB8);

// Configure SRAM mode
// EPIConfigHB8Set - all data transfers use bits[7:0]
ROM_EPIConfigHB8Set(EPI0_BASE, EPI_HB8_MODE_ADMUX | EPI_HB8_WRWAIT_0
| EPI_HB8_CSCFG_ALE | EPI_HB8_ALE_LOW
| EPI_HB8_RDWAIT_0 | EPI_HB8_CSCFG_CS, 0);


// Set the address map. Base 0x6000 0000, Using 1MB out of 16MB addr space
// Addr 0x6000 0000 - 1 Mbyte SRAM
// Addr 0x6010 0000 - 32Kx9 FIFO
ROM_EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_16MB | EPI_ADDR_RAM_BASE_6);

Thank you for your extremely quick response,

Joe

Hello Joe,

So now is it working? I tried the same on my setup and PK5 toggles as a clock

Regards
Amit

Hi Amit,

My ALE demux (~ '373) in my CPLD is not working properly. I noted that I set both EPI_HB8_CSCFG_ALE and EPI_HB8_CSCFG_CS for pin EPIS030. I fixed it as shown below, however I still receive a recurring pattern of bit errors. Is the entire EPI configuration OK now? I use A20 for the chip select, so it is always low when addressing the SRAM.

// Configure SRAM mode
// EPIConfigHB8Set - all data transfers use bits[7:0]
// ROM_EPIConfigHB8Set(EPI0_BASE, EPI_HB8_MODE_ADMUX | EPI_HB8_WRWAIT_0
// | EPI_HB8_CSCFG_ALE | EPI_HB8_ALE_LOW
// | EPI_HB8_RDWAIT_0 | EPI_HB8_CSCFG_CS, 0);

ROM_EPIConfigHB8Set(EPI0_BASE, EPI_HB8_MODE_ADMUX | EPI_HB8_WRWAIT_0
| EPI_HB8_CSCFG_ALE | EPI_HB8_ALE_LOW
| EPI_HB8_RDWAIT_0, 0); // 7-8-15

Thanks,

Joe

Hello Joe

Why are you using A20 for Chip Select when that is a separate signal in the ADMUX mode?

Regards
Amit

Hi Amit,

The SRAM utilizes addresses A19:A0 (1 Mbyte), so A20 is the next available address. When A20 is low it selects my SRAM; when high it selects my FIFO. It seems like a simple addressing scheme - that's why I chose it. Is there any disadvantages when using this with the TM4C129? (The ALE signal uses my CS on EPISO30).

Thanks,

Joe

Hello Joe,

Can you please share the schematics. It would be easier for me to correlate the code operation. Note that since this ADMUX the Address will not last for the entire cycle so the A20 may be lost after address phase.

Regards
Amit

Hi Amit,

I modified the circuit so that CS0 is wired to the SRAM, and CS1 to the FIFO. I am operating in the EPI_HB8_CSCFG_ALE_DUAL_CS mode. (I no longer use A20 as part of my chip select logic). After configuring the EPI pins for this mode, I do not receive a chip select on the SRAM. Here is the full EPI setup once again:

// Enable the EPI peripheral
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);

//---------------------------------------------------------------
// GPIO PORTS USED FOR EPI
//---------------------------------------------------------------

ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOP);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);



// Address Data Bus (AD7:AD0)
ROM_GPIOPinConfigure(GPIO_PK0_EPI0S0); // AD0
GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_0);

ROM_GPIOPinConfigure(GPIO_PK1_EPI0S1);
GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_1);

ROM_GPIOPinConfigure(GPIO_PK2_EPI0S2);
GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_2);

ROM_GPIOPinConfigure(GPIO_PK3_EPI0S3);
GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_3);

ROM_GPIOPinConfigure(GPIO_PC7_EPI0S4);
GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_7);

ROM_GPIOPinConfigure(GPIO_PC6_EPI0S5);
GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_6);

ROM_GPIOPinConfigure(GPIO_PC5_EPI0S6);
GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_5);

ROM_GPIOPinConfigure(GPIO_PC4_EPI0S7); // AD7
GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_4);

// Control Signals
ROM_GPIOPinConfigure(GPIO_PP3_EPI0S30); // nALE
GPIOPinTypeEPI(GPIO_PORTP_BASE, GPIO_PIN_3);

ROM_GPIOPinConfigure(GPIO_PP2_EPI0S29); // nWR
GPIOPinTypeEPI(GPIO_PORTP_BASE, GPIO_PIN_2);

ROM_GPIOPinConfigure(GPIO_PB3_EPI0S28); // nOE
GPIOPinTypeEPI(GPIO_PORTB_BASE, GPIO_PIN_3);

ROM_GPIOPinConfigure(GPIO_PK5_EPI0S31); // EPICLK
GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_5);

// S26 CS1 [PL4]
ROM_GPIOPinConfigure(GPIO_PL4_EPI0S26);
GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_4);


// S27 CS0 [PB2]
ROM_GPIOPinConfigure(GPIO_PB2_EPI0S27);
GPIOPinTypeEPI(GPIO_PORTB_BASE, GPIO_PIN_2);


// Address Bus (A20:A8)
ROM_GPIOPinConfigure(GPIO_PA6_EPI0S8); // A8
GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_6);

ROM_GPIOPinConfigure(GPIO_PA7_EPI0S9);
GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_7);

ROM_GPIOPinConfigure(GPIO_PG1_EPI0S10);
GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_1);

ROM_GPIOPinConfigure(GPIO_PG0_EPI0S11);
GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_0);

ROM_GPIOPinConfigure(GPIO_PM3_EPI0S12);
GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_3);

ROM_GPIOPinConfigure(GPIO_PM2_EPI0S13);
GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_2);

ROM_GPIOPinConfigure(GPIO_PM1_EPI0S14);
GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_1);

ROM_GPIOPinConfigure(GPIO_PM0_EPI0S15);
GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_0);

ROM_GPIOPinConfigure(GPIO_PL0_EPI0S16);
GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_0);

ROM_GPIOPinConfigure(GPIO_PL1_EPI0S17);
GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_1);

ROM_GPIOPinConfigure(GPIO_PL2_EPI0S18);
GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_2);

ROM_GPIOPinConfigure(GPIO_PL3_EPI0S19);
GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_3);

ROM_GPIOPinConfigure(GPIO_PQ0_EPI0S20);
GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_0); // A20





//---------------------------------------------------------------
// EPI Setup
//---------------------------------------------------------------

// Set the EPI divider.
ROM_EPIDividerSet(EPI0_BASE, 1); // Set to 1 (Do not set to 0)

// Select EPI Host Bus 8-bit mode.
ROM_EPIModeSet(EPI0_BASE, EPI_MODE_HB8);

// Configure SRAM mode
// EPIConfigHB8Set - all data transfers use bits[7:0]
ROM_EPIConfigHB8Set(EPI0_BASE, EPI_HB8_MODE_ADMUX | EPI_HB8_WRWAIT_0
| EPI_HB8_CSCFG_ALE_DUAL_CS | EPI_HB8_ALE_LOW // 7-13
| EPI_HB8_RDWAIT_0, 0); // 7-10-15 note - "2" wait states on both read and write

// Set the address map. Base 0x6000 0000, Using 1MB out of 16MB addr space
// Addr 0x6000 0000 - 1 Mbyte SRAM (cs0)
// Addr 0x6 - 32Kx9 FIFO (cs1)


ROM_EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_16MB | EPI_ADDR_RAM_BASE_6);

1) Why don't I have a CS0 chip select?

2) What would be the base address for the FIFO chip select?

(I refereed to the TM4C129x ROM User's Guide.)

Thanks,

Joe

 

Hello Joe,

I think this thread will explain the issue.

e2e.ti.com/.../431469

Can you enable the Peripheral region Address map by writing 0x99 to EPIADDRMAP and then accessing the address space of 0xA000.0000

Alternatively route the nCS1 to RAM Chip Select on the CPLD and vice versa for nCS0.

Regards
Amit

Hi Amit,

After swapping the addresses as you suggested, the SRAM  (unfortunately) behaves identical as when I used ADDR20 to select between the SRAM and the FIFO. The timing on the EPI bus does not appear as I expect. When I write 0x55 to all 1M locations I receive back a count - apparently the address feeding back into the data field. It would appear as if I have a configuration parameter incorrect.

Thanks,

Joe

Hello Joe,

I think we need to probe the signals going to the SRAM to see what is happening.

Regards
Amit

Hi Amit,

The wrong SRAM was received and installed on the board. Rather than a   IS61WV10248BLL-10TLI   it was a IS62WV10248DBLL-55TLI. The distributor mixed both parts in the same package that we received.

Thanks for your help, and sorry about the false alarm.

Joe

Hello Joe,

If it helps, I also made a similar mistake when instead of ordering the DBLL package I ordered the DALL package.

Regards
Amit

Feel not bad guys - this reporter (and smarter cohorts) have "bin boxes" filled w/Not quite "Good for Gov't Work" devices - ("off" by single char in most cases & discovered "too late" to return/exchange!) Hate when that happens - Devil delights in such detail...