Interfacing TMS570LC4357 with ADS8363

Werner,

I took a look at at the ADS8363 datasheet. I think that the ADS8363 CS pin should be tied low all the time. If you are using half clock mode, you can use SPI/CS pin to control both ADS8363 CONVST and RD pin. If the ADS8363 runs continuously in the application, I would recommend use SPI with DMA. You can set up a pinp-pong buffer with DMA to process the data. Are you reading data from two channels?

Thanks and regards,

Zhaohong

Thank you very much for your answer. I think my problem is that all three pins (/CS+RD+CONVST) are tied together and are connected to SPI CS. I will have to separate them. I want to read data from all eight single ended channels.

Right now:

TMS570LC4                 ADS

CS             --->              CS, RD, CONVST

CLK           --->              CLK

MOSI         --->              SDI

SDOA        --->              MISO0

SDOB        --->              MISO1

I scoped all pins and unfortunately on SDOA or SDOB no data came out. When I scoped the BUSY pin I noticed some activity going on.

My problem is that when I control RD and CONVST with the SPI CS, my ADS CS needs annother pin which I don't have.

Kindly regards,

Werner

On TMS570LC4357, the maximum data size on the SPI is 16 bit.  Given  this limitation, you need to set the ADS8363 to half clock mode with CID =0.  You need to start SPI transmission to generate the SPI clocks for reading.  If you are using the parallel mode to read 16 bit data from SDOA and SDOB, you will need to do the following.

(1)  Set the CSHOLD bit in the control field of the SPI_DAT1 register so that CS will stay low after transfer. Write to SPI_DAT1 register to generate clocks.

(2) Read from SPI_Buf register when data is ready. Bit 0-7 is the data from SDOA and bit 8-15 is from SDOB.

(3)  Clear the CSHOLD bit in the control field of the SPI_DAT1 register so that CS will go high after transfer. Write to SPI_DAT1 register to generate clocks.

(4) Read from SPI_Buf register when data is ready. Bit 0-7 is the data from SDOA and bit 8-15 is from SDOB.

For the configuration of the ADS8363, I would recommend not to enable the parallel mode. If you enable the parallel mode, you will need to split the 16 bit control data into two 8 bit data and follow the step described above.

This method requires CPU to do additional steps to reconstruct the 16 bit data for each channel.

The other option is to use two SPIs. One is configured as master to drive the clock and read from SDOA and the other one is configured as slave, reading SDOB. You can use the master to configure ADS.

Please check the SPI operation detail in the TRM. I think the it is fine to tie ADS CS pin low. It will not do anything until seeing the CONVST and RD signals.

Thanks and regards,

Zhaohong

Thank you very much for your answer but I still don't know if I can use the ADS8363 with the three ADS pins (/CS+RD+CONVST) tied together with TMS570LC4 CS. When do you know in (2) when data is ready?
Thanks and regards,
Werner

I do not think that you can hook all three pins (CS+RD+CONVST) to SPI CS. You can tie ADS CS low gto have it enabled all the time. ADS will not do anything until CONVST and RD signals are active.

You can set up SPI to generate an interrupt or When data is ready, SPI will generate an interrupt or DMA request.

Another thought. Please check if the A/D sampling needs to be repeated at the precise time intervals. If the answer is yes, you need to use a timer to generate a pulse to trigger CONVST so that A/D sample s are taken at exact time interval.

Thanks and regards,

Zhaohong

Hello Zhaohong,

I put the /CS of the ADS to GND and the TMS CS I connected to RD+CONVST. Now I have two problems:

The CS of the TMS which is now connected to RD+CONVST is inactive (high) too long. In the data sheet is said

max. time is 1 clockcycle. How can I shorten it?

The second problem is my clock which is stopping during CS inactive. This way the RD+CONVST is never

detected because it sees neither a rising nor a falling edge. What could I do?

Best regards,

Werner

By SPI standard, the clock is only active during data transfer. It is not active when the SPI CS is high. One option to solve this issue is to use the the rising edge of the SPI CS to trigger a small pulse. The pulse needs to short so that it goes low before SPI CS goes low. This pulse and SPI ClK will be connected to ADS CS via an OR gate. Since it is just one pulse (one clock period), I also solves the pulse width issue for ADS convst and rd.

Thanks and regards,

Zhaohong