Hi everyone,
I'm a bit stuck on setting up a uDMA transfer. I want to transfer 32 bits of data from the SSI3 data register to a buffer.
I have still enabled the SSI3 RXIM interrupt as its my understanding that this is where the udma interrupt will go to.
When I execute the code I am going into the interrupt handler but it is the SSI3 receive interrupt that is firing not the udma transfer complete interrupt.
I realise my interrupt handler is missing code to restart the transfer.
can anyone offer me some guidance? I feel like I have missed something fundamental.
uint32_t ucControlTable[256] __attribute__ ((aligned(1024))); //Control Table for uDMA
volatile uint32_t InputStreamPtr[256];
void initSSI3(void)
{
SYSCTL->RCGCSSI |= 0x00000008; //enable clock gating
vDelayX(5);
SSI3->CR1 &= ~SSI_CR1_SSE; // disable operation when changing bits
SSI3->CR1 |= SSI_CR1_MS; // set as slave
SSI3->CC = SSI_CC_CS_SYSPLL; // system clock
SSI3->CPSR = 0x62; // BR=SysClk/(CPSDVSR * (1 + SCR)) => 127551 = 50000000 / (98d*(1+3))
SSI3->CR0 |= SSI_CR0_FRF_TI;
SSI3->CR0 |= SSI_CR0_DSS_16; // 16 bit data size
SSI3->CR0 |= 0x03 << 8; // BR=SysClk/(CPSDVSR * (1 + SCR)) => 127551 = 50000000 / (98d*(1+3))
while(0 != (uiClearData == SSI3->DR));
}
void initUdma(void)
{
SYSCTL->RCGCDMA = 0x01; //enable uDMA clock
vDelayX(5); //wait
UDMA->CFG = 0x00000001; //Enable uDMA controller
UDMA->CTLBASE = (uint32_t)ucControlTable; //Base address for channel control
UDMA->CHMAP1 = (UDMA->CHMAP1&0xF0FFFFFF)|0x01000000; //Channel 14 used
UDMA->PRIOCLR = (1UL<<14); //Channel 14 default priority
UDMA->ALTCLR = (1UL<<14); //Channel 14 primary control
UDMA->USEBURSTCLR = (1UL<<14); //Allow burst and single request response
UDMA->REQMASKCLR = (1UL<<14); //recognise requests for channel 14
ucControlTable[CH14PR] = (uint32_t)SSI3->DR; //rx from peripheral and put to txdestptr
ucControlTable[CH14PR+4] = (uint32_t)InputStreamPtr;
ucControlTable[CH14PR+8] = 0x5D004001;
/* DMACHCTL Bits Value Description
DSTINC 31:30 01 destination address increment by 16 bits
DSTSIZE 29:28 01 16-bit destination data size
SRCINC 27:26 11 no source address increment
SRCSIZE 25:24 01 16-bit source data size
reserved 23:18 000000 N/A
ARBSIZE 17:14 0001 Arbitrates after 2 transfer
XFERSIZE 13:4 0000000000 Transfer count items
NXTUSEBURST 3 0 N/A
XFERMODE 2:0 001 Use basic transfer mode
*/
SSI3->DMACTL = (1UL<<0); // set dma ctrl for rx fifo - set after dma set up
UDMA->ENASET |= (1UL<<14); //| (1UL<<15);
}
void startSSI3(void)
{
SSI3->CR1 |= SSI_CR1_SSE; // enable operation
while(0 != (uiClearData == SSI3->DR)); // empty receive fifo
SSI3->IM = SSI_IM_RXIM;
SSI3->ICR = SSI_IM_RXIM;
}
void vSSI3InterruptHandler(void)
{
unsigned int uiDataReceive;
SSI3->ICR = SSI_IM_RXIM;
//uiDataReceive = SSI3->DR;
//SSI3->DR = uiDataReceive;
//while(!(SSI1->SR & SSI_SR_TFE)); //old loopback code
}
Thanks
Sarah
