Hercules RM48L952ZWT Flash Erase Does not Work Using FAPI API

Hi Anthony. Thank you. Since the sample bootloader code didn't have it I just assumed there was a reason. 

For the Fapi_enableMainBankSectors() function the pdf does not go into any detail -- for enabling bank 0 and bank 1, what should the value of the argument be?

i.e., for Bank 0 is it Fapi_enableMainBankSectors(0) and Bank 1 Fapi_enableMainBankSectors(1)? Or i.e., Fapi_enableMainBankSectors(0xFFF0) for all sectors minus what are reserved for bootloader in first 4 sectors of bank 0 and for bank 1 = Fapi_enableMainBankSectors(0xFFF1)?

 Thank you again

Hi Anthony. I wanted to add that the code that came by default with the uart bootloader from TI also fails at this same initialization function as above (which is why I tried doing a variant of it). The zip file uploaded here of TI uart bootloader:  3872.SafetyMCU_Bootloader_Original_FlashIssue.zip

(copy paste from bl_flash.c)

uint32_t Fapi_BlockErase( uint32_t Bank, uint32_t Erase_Start_Address, uint32_t Size_In_Bytes)

{

uint32_t status;

uint32_t Freq_In_MHz;

uint8_t  i, j, bk, ucStartBank, ucStartSector, ucEndBank;

uint32_t *eraseStartAddr0;

uint32_t *eraseStartAddr;

   int  remaining, GET_FSM_STATUS;

   uint32_t Erase_End_Address;

ucStartBank = 0, i=0, ucStartSector = 0;

ucEndBank = 0;

eraseStartAddr0 = (uint32_t *)Erase_Start_Address;

eraseStartAddr = (uint32_t *)Erase_Start_Address;

Erase_End_Address = Erase_Start_Address + Size_In_Bytes;

Freq_In_MHz = SYS_CLK_FREQ;

for (i = 0; i < NUMBEROFSECTORS-1; i++){

if (Erase_Start_Address == (uint32_t)(flash_sector[i].start))

{

ucStartBank     = flash_sector[i].bankNumber;

   ucStartSector   = flash_sector[i].sectorNumber;

   eraseStartAddr0 = flash_sector[i].start;

   eraseStartAddr  = flash_sector[i].start;

   break;

}

}

for (i = ucStartSector; i < NUMBEROFSECTORS-1; i++){

if (Erase_End_Address <= ((uint32_t)(flash_sector[i].start) + flash_sector[i].length))

{

ucEndBank   = flash_sector[i].bankNumber;

   break;

}

}

//F021_CPU0_REGISTER_ADDRESS is defined as 0xfff87000 in FMC.h

//Fapi_initializeAPI((Fapi_FmcRegistersType *)F021_CPU0_REGISTER_ADDRESS, Freq_In_MHz); /*used for API Rev1.5*/

status=Fapi_initializeFlashBanks(Freq_In_MHz); /* used for API Rev2.01 */

   for (bk = ucStartBank; bk < (ucEndBank + 1); bk++){

       status=Fapi_setActiveFlashBank((Fapi_FlashBankType)bk);

    if (bk == 0){

       j = ucStartSector;

       remaining = Size_In_Bytes;

    }else{

       j = 0;

    }

       status= Fapi_enableMainBankSectors(0xFFFF);        /* used for API 2.01*/

       while( FAPI_CHECK_FSM_READY_BUSY != Fapi_Status_FsmReady );

    do{

    status= Fapi_issueAsyncCommandWithAddress(Fapi_EraseSector, eraseStartAddr);

        while( FAPI_CHECK_FSM_READY_BUSY == Fapi_Status_FsmBusy );

        while(FAPI_GET_FSM_STATUS != Fapi_Status_Success);

           remaining -= flash_sector[j++].length;

    eraseStartAddr = flash_sector[j].start;

       }while((remaining > 0) && ( j < flash_bank[bk].numOfSectors));

   }

status =  Flash_Erase_Check((uint32_t)eraseStartAddr0, Size_In_Bytes);

return (status);

}

Hi Anthony. Thank you. It fails at function Fapi_initializeFlashBanks  and I tried for both frequences 200 and 160. This is the API that came integrated with the TI bootloader here: 0488.SafetyMCU_Bootloader_Original_FlashIssue.zip

Yes, please.

If it does read correctly then please add some code in your "C" file before you make the API call to read the same location.  (In case the issue is with the CPU's privilegle level when the API is called - it'll show as a problem if your read it in code but not through the debugger).

Best Regards,

Anthony

Tammy,

The TRM  http://www.ti.com/lit/ug/spnu503b/spnu503b.pdf

5.7.1 Flash Option Control Register (FRDCNTL)      address FFF87000h - RWAIT is bits 11:8 and pipeline mode is enabled by setting bit 0.   (You need pipeline mode to operate at 160MHz or 200MHz)

5.7.34 EEPROM Emulation Configuration Register (EEPROM_CONFIG) FFF872B8h - Ewait is in bits 19:16.

The datasheet:

has  a section 5.6 Wait States Required - which tells you how many wait states are needed to operate at a given frquency.   You need 3 data wait states to operate at 200 or 220MHz according to this table, plus an extra wait state when the address changes 'randomly' (not sequentally)

EDIT:  HalCoGen normally sets the wait states based on your PLL frequency and it's done during the initialization of the device,  before getting to main() - so it may be that the bootloader example from us that you're looking at expects this is already done.   [I haven't looked at the bootloader code you sent].   

Anyway I think the next step is to make sure the OTP is readable and that the wait states are programmed.  At least one of these should be a 'no' and that'll be the one to fix.

Hi Anthony. Thank you.

** Reading from CCS debugger "Registers. FlashWrapper->FRdCntl = 0x00000311 so ENPIPE(bit 0) = 1, ASWSTEN(bit 4) = 1 and RWAIT (bits 8 - 11) = 3. It is set in the system.c file I uploaded for you in the setupFlash() function. Does this look correct to you?

** I can confirm that in the CCS Debugger Memory Browser, 0xF008017C (and later values) show up as "--------" in CCS. So does this mean we cannot read the correct value out of the OTP? How is this resolved? Thank you again

Hi Tammy,

FRdCntl value looks correct for > 160MHz.   So that's good.

I forgot that CCS has a memory map too (it's independent of the software you write for the part).

If you've just used the default target configuration - which I've snapped a screenshot of here:

You can see by clicking on the advanced tab and picking the Cortex R4 node that the R4 uses a GEL file which is displayed on the right hand pane.

The GEL file defines a memory map for CCS to use - it's main purpose is to avoid having CCS cause an error by say letting you scroll a memory view window into an area of the memory map that would create an exception -- or to prevent you from writing to an area that is read only and causing an exception.  

If a memory map region isn't listed, and you have the memory mapping turned on (which it should be by default) you'll get the '---' in the memory view when you inspect through CCS.

I notice in my copy of the Rm48L952 GEL which should be 'stock' that the TI OTP isn't included:

    /* Other Flash Related Memories*/
    GEL_MapAdd(0xF0200000, 0, 0x00010000, 1, 0); /* EEPROM                      */
    GEL_MapAddStr(0xF0100000, 0, 0x00002000, "R|AS2", 0); /* EEPROM    ECC                  */
    GEL_MapAdd(0xF0000000, 0, 0x00004000, 1, 0); /* Customer OTP                      */
    GEL_MapAddStr(0xF0040000, 0, 0x00000800, "R|AS2", 0); /* Customer OTP ECC          */
    GEL_MapAdd(0xF000E000, 0, 0x00001000, 1, 0); /* Customer OTP, EEPROM              */
    GEL_MapAddStr(0xF0041C00, 0, 0x00000400, "R|AS2", 0); /* Customer OTP, EEPROM ECC          */

So choices...

  1) Now that we know your wait states are correct it's pretty likely that there is an MPU setting at work preventing the CPU from reading the TI OTP region.

     So you could skip to it and just add a line of code to your project that reads from 0xF008017C like:

     tmp = *((volatile unsigned int *)0xF008017C);  before the call to the API funciton.

    Then see what value the CPU gets for tmp.. or if it gets an abort.

  2) You could also add the region to your memory map in CCS so you can check through the debugger.   The debugger though usually is given privilege so it is possible you can read the area with the debugger but not with the CPU as you have it configured.
Still it's a good way to see what is actually in the flash ..

    You could add this line to the GEL file.

     GEL_MapAdd(0xF0080000, 0, 0x00004000, 1, 0); /* TI OTP                      */

  (add it under the Customer OTP )  then save the gel file,  terminate the debug session and start another.

  or if you want to avoid modifying the GEL file you can make a one-time change by using the Scripting Console in CCS.

You can type:  

    mmEnable(true)

    mmAdd(0xF008000,0,0x4000,true,false)

and then check the region again in the memory viewer.

Tammy,

mmEnable() and mmAdd() commands go in the Scripting Console of CCS.

type at the js> prompt.

Best Regards,

Anthony

Tammy,

I talked to my neighbor about this who's familiar w. the OTP setting and 01Ch is right. Even though I mentioned I thought it would be something like '45MHz'... a) you are on a 220MHz part so it's rated to 56MHz flash, and b) the OTP value multiplied by 2 before it's divided into 220MHz.

So the test is 220MHz / ((3+1)*2) > 28 and even with rounding this should be testing 28>28 and returning the Fapi_Error_InvalidHclkValue if it evaluates to 'true'. ['3' is your RWAIT value - 3 = 4 wait states]. EDIT: 28>28 should evaluate 'false'... which is why you shouldn't get Fapi_Error_InvalidHclkValue...

So it doesn't seem that you should be getting Fapi_Error_InvalidHclkValue with the settings you have and operation on the main banks.

However, if the bank you accessing is set to FlashBank7 then it would be using the EWAIT register in the test not the RWAIT register. So it would be good to check what the EWAIT register is set to and to confirm that you're not operating on Bank 7 accidentally.

Worst case we may need to figure out how to step through the object code and see why the test is returning that value... which is doable even w.o. the source but it'd be my last resort.

Best Regards,
Anthony

Tammy,

I downloaded your zip file, and in the DEBUG folder ran this command:

C:\Users\a0321811\Desktop\SafetyMCU_Bootloader_Original\RM48\boot_uart\Debug>c:\ti\ccsv6\tools\compiler\ti-cgt-arm_5.2.4\bin\armdis.exe --all boot_uart_RM48_Original.out > disasm.txt

To generate the disassembly of the program so I could look at the code for the function Fapi_initializeFlashBanks.

You may need to repeat that step if you have rebuilt since you uploaded the ZIP file and the addresses differ.

Ok then based on the enum in   \inc\F021_API\types.h, I gather that the error code Fapi_Error_InvalidHclkValue you get has a value of 8:

typedef enum
{
   Fapi_Status_Success=0,           /* Function completed successfully */
   Fapi_Status_FsmBusy,             /* FSM is Busy */
   Fapi_Status_FsmReady,            /* FSM is Ready */
   Fapi_Error_Fail,                 /* Generic Function Fail code */
   Fapi_Error_NullPointer,          /* One of the pointer parameters is a null pointer */
   Fapi_Error_InvalidCommand,       /* Command used is invalid for the function called */
   Fapi_Error_InvalidEccAddress,    /* Returned if the ECC Address given to a function is invalid for that function */
   Fapi_Error_OtpChecksumMismatch,  /* Returned if OTP checksum does not match expected value */
   Fapi_Error_InvalidHclkValue,     /* Returned if FClk is above max FClk value - FClk is a calculated from HClk and 
                                       RWAIT/EWAIT */

Looking at the disassembly for the function, I found the place where it would set the return value to #8 and then basically exit.  Marked in yellow with key lines in Red. [EDIT - wasn't readable w. colors so I commented instead, look down near address 80028fa, my comments are <<< in the right columns..]

8002858:              Fapi_initializeFlashBanks:
8002858:               .thumb
8002858:              .text:Fapi_initializeFlashBanks:
8002858: 2DE9F047         STMDB.W         R13!, {R4, R5, R6, R7, R8, R9, R10, R14}
800285c: 0646             MOV             R6, R0
800285e: ADF1600D         SUB.W           R13, R13, #96
8002862: 0A2E             CMP             R6, #10
8002864: C0F01C81         BCC.W           0x08002AA0
8002868: 8F4C             LDR             R4, $C$CON2 [0x8002aa8]
800286a: 1821             MOVS            R1, #24
800286c: 8F4A             LDR             R2, $C$CON3 [0x8002aac]
800286e: 2068             LDR             R0, [R4]
8002870: 4C3C             SUBS            R4, #76
8002872: 40F00700         ORR.W           R0, R0, #7
8002876: E064             STR             R0, [R4, #76]
8002878: 6846             MOV             R0, R13
800287a:              $C$L2:
800287a: 52F8043B         LDR.W           R3, [R2], #4
800287e: 491E             SUBS            R1, R1, #1
8002880: 40F8043B         STR.W           R3, [R0], #4
8002884: F9D1             BNE             0x0800287A
8002886: 139F             LDR             R7, [SP, #76]
8002888: DDF82C80         LDR.W           R8, [R13, #44]
800288c: 08A8             ADD             R0, SP, #32 
800288e: 54F8045C         LDR.W           R5, [R4, #-4]
8002892: 1621             MOVS            R1, #22
8002894: D4F8B492         LDR.W           R9, [R4, #692]
8002898: 00F0DEFA         BL              0x08002E58
800289c: 8742             CMP             R7, R0
800289e: C9F30341         UBFX.W          R1, R9, #16, #4
80028a2: C5F30325         UBFX.W          R5, R5, #8, #4
80028a6: C8F30B09         UBFX.W          R9, R8, #0, #12
80028aa: 05F10105         ADD.W           R5, R5, #1
80028ae: 01F10108         ADD.W           R8, R1, #1
80028b2: 24D1             BNE             0x080028FE
80028b4: 3046             MOV             R0, R6
80028b6: 6900             LSLS            R1, R5, #1
80028b8: 00F099FB         BL              0x08002FEE
80028bc: 4FEA061A         MOV.W           R10, R6, LSL #4
80028c0: 2946             MOV             R1, R5
80028c2: 0746             MOV             R7, R0
80028c4: 5046             MOV             R0, R10
80028c6: 00F092FB         BL              0x08002FEE
80028ca: 00F0B1FB         BL              0x08003030
80028ce: B945             CMP             R9, R7
80028d0: 13D3             BCC             0x080028FA
80028d2: 3046             MOV             R0, R6
80028d4: 4FEA4801         MOV.W           R1, R8, LSL #1
80028d8: 00F089FB         BL              0x08002FEE
80028dc: 4146             MOV             R1, R8
80028de: 0546             MOV             R5, R0
80028e0: 5046             MOV             R0, R10
80028e2: 00F084FB         BL              0x08002FEE
80028e6: 00F09BFB         BL              0x08003020
80028ea: 7148             LDR             R0, $C$CON4 [0x8002ab0]
80028ec: 0068             LDR             R0, [R0]
80028ee: 6FF31F30         BFC.W           R0, #12, #20
80028f2: 8542             CMP             R5, R0               <<< THIS SHOULD BE TESTING 28 > 28
80028f4: 98BF             IT              LS
80028f6: 0020             MOVLS           R0, #0
80028f8: 02D9             BLS             0x08002900
80028fa:              $C$L3:
80028fa: 0820             MOVS            R0, #8               <<< THIS SHOULD BE YOUR ERROR
80028fc: 00E0             B               0x08002900
80028fe:              $C$L4:
80028fe: 0720             MOVS            R0, #7
8002900:              $C$L5:
8002900: 0028             CMP             R0, #0
8002902: 40F0C480         BNE.W           0x08002A8E
8002906: 2168             LDR             R1, [R4]
8002908: 0527             MOVS            R7, #5
800290a: 4AF65525         MOVW.W          R5, #43605
800290e: 4FF48A46         MOV.W           R6, #17664
8002912: 40F20313         MOVW.W          R3, #259
8002916: 21F47F41         BIC.W           R1, R1, #65280
800291a: 2160             STR             R1, [R4]
800291c: 2168             LDR             R1, [R4]
800291e: 21F00101         BIC.W           R1, R1, #1
8002922: 2160             STR             R1, [R4]
8002924: 2168             LDR             R1, [R4]
8002926: 21F00201         BIC.W           R1, R1, #2
800292a: 2160             STR             R1, [R4]
800292c: C4F88472         STR.W           R7, [R4, #644]
8002930: 0899             LDR             R1, [SP, #32]
8002932: D4F80C22         LDR.W           R2, [R4, #524]
8002936: 5F4F             LDR             R7, $C$CON5 [0x8002ab4]
8002938: 0916             ASRS            R1, R1, #24
800293a: 61F30F22         BFI.W           R2, R1, #8, #8
800293e: C4F80C22         STR.W           R2, [R4, #524]
8002942: 0899             LDR             R1, [SP, #32]
8002944: D4F80C22         LDR.W           R2, [R4, #524]
8002948: 0914             ASRS            R1, R1, #16
800294a: 61F30702         BFI.W           R2, R1, #0, #8
800294e: C4F80C22         STR.W           R2, [R4, #524]
8002952: 0899             LDR             R1, [SP, #32]
8002954: D4F81422         LDR.W           R2, [R4, #532]
8002958: 0912             ASRS            R1, R1, #8
800295a: 61F30F22         BFI.W           R2, R1, #8, #8
800295e: C4F81422         STR.W           R2, [R4, #532]
8002962: 089A             LDR             R2, [SP, #32]
8002964: D4F81412         LDR.W           R1, [R4, #532]
8002968: 62F30701         BFI.W           R1, R2, #0, #8
800296c: C4F81412         STR.W           R1, [R4, #532]
8002970: 099A             LDR             R2, [SP, #36]
8002972: D4F81812         LDR.W           R1, [R4, #536]
8002976: 62F30B01         BFI.W           R1, R2, #0, #12
800297a: C4F81812         STR.W           R1, [R4, #536]
800297e: 0999             LDR             R1, [SP, #36]
8002980: D4F81822         LDR.W           R2, [R4, #536]
8002984: 0913             ASRS            R1, R1, #12
8002986: 61F30F32         BFI.W           R2, R1, #12, #4
800298a: C4F81822         STR.W           R2, [R4, #536]
800298e: 0B99             LDR             R1, [SP, #44]
8002990: D4F81022         LDR.W           R2, [R4, #528]
8002994: 0913             ASRS            R1, R1, #12
8002996: 61F30F32         BFI.W           R2, R1, #12, #4
800299a: C4F81022         STR.W           R2, [R4, #528]
800299e: 0999             LDR             R1, [SP, #36]
80029a0: D4F81C22         LDR.W           R2, [R4, #540]
80029a4: 0916             ASRS            R1, R1, #24
80029a6: 61F30F22         BFI.W           R2, R1, #8, #8
80029aa: C4F81C22         STR.W           R2, [R4, #540]
80029ae: 0A99             LDR             R1, [SP, #40]
80029b0: D4F82022         LDR.W           R2, [R4, #544]
80029b4: 0914             ASRS            R1, R1, #16
80029b6: 61F30702         BFI.W           R2, R1, #0, #8
80029ba: C4F82022         STR.W           R2, [R4, #544]
80029be: 0D9A             LDR             R2, [SP, #52]
80029c0: D4F86412         LDR.W           R1, [R4, #612]
80029c4: 62F30B01         BFI.W           R1, R2, #0, #12
80029c8: C4F86412         STR.W           R1, [R4, #612]
80029cc: 109A             LDR             R2, [SP, #64]
80029ce: D4F86812         LDR.W           R1, [R4, #616]
80029d2: 62F31841         BFI.W           R1, R2, #16, #9
80029d6: C4F86812         STR.W           R1, [R4, #616]
80029da: D4F86C12         LDR.W           R1, [R4, #620]
80029de: 6FF31841         BFC.W           R1, #16, #9
80029e2: C4F86C12         STR.W           R1, [R4, #620]
80029e6: 0C99             LDR             R1, [SP, #48]
80029e8: D4F87422         LDR.W           R2, [R4, #628]
80029ec: 491E             SUBS            R1, R1, #1
80029ee: 61F30602         BFI.W           R2, R1, #0, #7
80029f2: C4F87422         STR.W           R2, [R4, #628]
80029f6: C4F87862         STR.W           R6, [R4, #632]
80029fa: 226E             LDR             R2, [R4, #96]
80029fc: 0026             MOVS            R6, #0
80029fe: 6FF30F02         BFC.W           R2, #0, #16
8002a02: 45EA0201         ORR.W           R1, R5, R2
8002a06: 2166             STR             R1, [R4, #96]
8002a08: 129A             LDR             R2, [SP, #72]
8002a0a: E16F             LDR             R1, [R4, #124]
8002a0c: 1212             ASRS            R2, R2, #8
8002a0e: 62F30301         BFI.W           R1, R2, #0, #4
8002a12: E167             STR             R1, [R4, #124]
8002a14: C4F88860         STR.W           R6, [R4, #136]
8002a18: C4F8FC70         STR.W           R7, [R4, #252]
8002a1c: C4F80031         STR.W           R3, [R4, #256]
8002a20: C4F80461         STR.W           R6, [R4, #260]
8002a24: D4F80811         LDR.W           R1, [R4, #264]
8002a28: 21F07F01         BIC.W           R1, R1, #127
8002a2c: C4F80811         STR.W           R1, [R4, #264]
8002a30: 1199             LDR             R1, [SP, #68]
8002a32: D4F88C50         LDR.W           R5, [R4, #140]
8002a36: 0912             ASRS            R1, R1, #8
8002a38: 61F30C25         BFI.W           R5, R1, #8, #5
8002a3c: C4F88C50         STR.W           R5, [R4, #140]
8002a40: 119D             LDR             R5, [SP, #68]
8002a42: D4F88C10         LDR.W           R1, [R4, #140]
8002a46: 65F30401         BFI.W           R1, R5, #0, #5
8002a4a: C4F88C10         STR.W           R1, [R4, #140]
8002a4e: 1299             LDR             R1, [SP, #72]
8002a50: D4F89050         LDR.W           R5, [R4, #144]
8002a54: 0916             ASRS            R1, R1, #24
8002a56: 61F30F35         BFI.W           R5, R1, #12, #4
8002a5a: C4F89050         STR.W           R5, [R4, #144]
8002a5e: 1299             LDR             R1, [SP, #72]
8002a60: D4F89450         LDR.W           R5, [R4, #148]
8002a64: 0914             ASRS            R1, R1, #16
8002a66: 61F30405         BFI.W           R5, R1, #0, #5
8002a6a: C4F89450         STR.W           R5, [R4, #148]
8002a6e: 0B99             LDR             R1, [SP, #44]
8002a70: D4F8A450         LDR.W           R5, [R4, #164]
8002a74: 0914             ASRS            R1, R1, #16
8002a76: 61F30705         BFI.W           R5, R1, #0, #8
8002a7a: C4F8A450         STR.W           R5, [R4, #164]
8002a7e: C4F80031         STR.W           R3, [R4, #256]
8002a82: C4F8FC70         STR.W           R7, [R4, #252]
8002a86: 216E             LDR             R1, [R4, #96]
8002a88: 6FF30F01         BFC.W           R1, #0, #16
8002a8c: 2166             STR             R1, [R4, #96]
8002a8e:              $C$L6:
8002a8e: D4F88412         LDR.W           R1, [R4, #644]
8002a92: 21F00701         BIC.W           R1, R1, #7
8002a96: 41F00201         ORR.W           R1, R1, #2
8002a9a: C4F88412         STR.W           R1, [R4, #644]
8002a9e: 00E0             B               0x08002AA2
8002aa0:              $C$L7:
8002aa0: 0820             MOVS            R0, #8
8002aa2:              $C$L8:
8002aa2: 18B0             ADD             SP, #96
8002aa4: BDE8F087         LDMIA.W         R13!, {R4, R5, R6, R7, R8, R9, R10, PC}
8002aa8:              $d:
8002aa8:              $C$CON2:
8002aa8: 5070            .half		 0x7050
8002aaa: F8FF            .half		 0xFFF8
8002aac:              $C$CON3:
8002aac: 5001            .half		 0x0150
8002aae: 08F0            .half		 0xF008
8002ab0:              $C$CON4:
8002ab0: 7CE1            .half		 0xE17C
8002ab2: 08F0            .half		 0xF008
8002ab4:              $C$CON5:
8002ab4: 0401            .half		 0x0104
8002ab6: 0100            .half		 0x0001
8002ab8:              Fapi_setActiveFlashBank:
8002ab8:               .thumb
8002ab8:              .text:Fapi_setActiveFlashBank:
8002ab8: 2DE9F843         STMDB.W         R13!, {R3, R4, R5, R6, R7, R8, R9, R14}
8002abc: 5A4D             LDR             R5, $C$CON1 [0x8002c28]
8002abe: DFF86C81         LDR.W           R8, [PC, #364]
8002ac2: 2968             LDR             R1, [R5]
8002ac4: 01F00701         AND.W           R1, R1, #7
8002ac8: 8142             CMP             R1, R0
8002aca: 4146             MOV             R1, R8
8002acc: 05D1             BNE             0x08002ADA
8002ace: 0978             LDRB            R1, [R1]
8002ad0: 0029             CMP             R1, #0
8002ad2: 08BF             IT              EQ
8002ad4: 0020             MOVEQ           R0, #0
8002ad6: 00F0A480         BEQ.W           0x08002C22
8002ada:              $C$L1:
8002ada: 2A68             LDR             R2, [R5]
8002adc: 2968             LDR             R1, [R5]
8002ade: 544C             LDR             R4, $C$CON3 [0x8002c30]
8002ae0: 02F00702         AND.W           R2, R2, #7
8002ae4: 60F30201         BFI.W           R1, R0, #0, #3
8002ae8: 2960             STR             R1, [R5]
8002aea: C4EB4034         RSB.W           R4, R4, R0, LSL #13
8002aee: 2968             LDR             R1, [R5]
8002af0: 01F00701         AND.W           R1, R1, #7
8002af4: 8842             CMP             R0, R1
8002af6: 40F08C80         BNE.W           0x08002C12
8002afa: 216C             LDR             R1, [R4, #64]
8002afc: 226C             LDR             R2, [R4, #64]
8002afe: 0B04             LSLS            R3, R1, #16
8002b00: 616C             LDR             R1, [R4, #68]
8002b02: 170C             LSRS            R7, R2, #16
8002b04: 0728             CMP             R0, #7
8002b06: 4FEA1146         MOV.W           R6, R1, LSR #16
8002b0a: 4FEA1349         MOV.W           R9, R3, LSR #16
8002b0e: 03D1             BNE             0x08002B18
8002b10: 0020             MOVS            R0, #0
8002b12: 00F085FA         BL              0x08003020
8002b16: 02E0             B               0x08002B1E
8002b18:              $C$L2:
8002b18: 0020             MOVS            R0, #0
8002b1a: 00F089FA         BL              0x08003030
8002b1e:              $C$L3:
8002b1e: D5F83812         LDR.W           R1, [R5, #568]
8002b22: 21F00301         BIC.W           R1, R1, #3
8002b26: 41F00501         ORR.W           R1, R1, #5
8002b2a: C5F83812         STR.W           R1, [R5, #568]
8002b2e: A16B             LDR             R1, [R4, #56]
8002b30: 6FF31F41         BFC.W           R1, #16, #16
8002b34: D5F8F021         LDR.W           R2, [R5, #496]
8002b38: 4143             MULS            R1, R0
8002b3a: 8902             LSLS            R1, R1, #10
8002b3c: 6FF30F02         BFC.W           R2, #0, #16
8002b40: 42EA1142         ORR.W           R2, R2, R1, LSR #16
8002b44: C5F8F021         STR.W           R2, [R5, #496]
8002b48: E16B             LDR             R1, [R4, #60]
8002b4a: 4143             MULS            R1, R0
8002b4c: 8909             LSRS            R1, R1, #6
8002b4e: C5F8F411         STR.W           R1, [R5, #500]
8002b52: 616A             LDR             R1, [R4, #36]
8002b54: C1F30741         UBFX.W          R1, R1, #16, #8
8002b58: 4143             MULS            R1, R0
8002b5a: D5F8D021         LDR.W           R2, [R5, #464]
8002b5e: 8911             ASRS            R1, R1, #6
8002b60: 61F30702         BFI.W           R2, R1, #0, #8
8002b64: C5F8D021         STR.W           R2, [R5, #464]
8002b68: A16A             LDR             R1, [R4, #40]
8002b6a: 090E             LSRS            R1, R1, #24
8002b6c: 4143             MULS            R1, R0
8002b6e: D5F8D821         LDR.W           R2, [R5, #472]
8002b72: 8911             ASRS            R1, R1, #6
8002b74: 61F30F22         BFI.W           R2, R1, #8, #8
8002b78: C5F8D821         STR.W           R2, [R5, #472]
8002b7c: E16A             LDR             R1, [R4, #44]
8002b7e: 090E             LSRS            R1, R1, #24
8002b80: 4143             MULS            R1, R0
8002b82: D5F8DC21         LDR.W           R2, [R5, #476]
8002b86: 8902             LSLS            R1, R1, #10
8002b88: 6FF30F02         BFC.W           R2, #0, #16
8002b8c: 42EA1142         ORR.W           R2, R2, R1, LSR #16
8002b90: C5F8DC21         STR.W           R2, [R5, #476]
8002b94: A16A             LDR             R1, [R4, #40]
8002b96: C1F30721         UBFX.W          R1, R1, #8, #8
8002b9a: 4843             MULS            R0, R1
8002b9c: D5F8E431         LDR.W           R3, [R5, #484]
8002ba0: 8011             ASRS            R0, R0, #6
8002ba2: 60F30F23         BFI.W           R3, R0, #8, #8
8002ba6: C5F8E431         STR.W           R3, [R5, #484]
8002baa: 206B             LDR             R0, [R4, #48]
8002bac: D5F81812         LDR.W           R1, [R5, #536]
8002bb0: 0014             ASRS            R0, R0, #16
8002bb2: 60F31841         BFI.W           R1, R0, #16, #9
8002bb6: C5F81812         STR.W           R1, [R5, #536]
8002bba: A16B             LDR             R1, [R4, #56]
8002bbc: D5F81C02         LDR.W           R0, [R5, #540]
8002bc0: 0901             LSLS            R1, R1, #4
8002bc2: 6FF30B00         BFC.W           R0, #0, #12
8002bc6: 40EA1150         ORR.W           R0, R0, R1, LSR #20
8002bca: C5F81C02         STR.W           R0, [R5, #540]
8002bce: 6969             LDR             R1, [R5, #20]
8002bd0: 4AF65522         MOVW.W          R2, #43605
8002bd4: 6FF30F01         BFC.W           R1, #0, #16
8002bd8: 42EA0100         ORR.W           R0, R2, R1
8002bdc: 6861             STR             R0, [R5, #20]
8002bde: 686B             LDR             R0, [R5, #52]
8002be0: 69F31840         BFI.W           R0, R9, #16, #9
8002be4: 6863             STR             R0, [R5, #52]
8002be6: 686B             LDR             R0, [R5, #52]
8002be8: 66F30800         BFI.W           R0, R6, #0, #9
8002bec: 6863             STR             R0, [R5, #52]
8002bee: A86B             LDR             R0, [R5, #56]
8002bf0: 67F31840         BFI.W           R0, R7, #16, #9
8002bf4: A863             STR             R0, [R5, #56]
8002bf6: 6869             LDR             R0, [R5, #20]
8002bf8: 6FF30F00         BFC.W           R0, #0, #16
8002bfc: 6861             STR             R0, [R5, #20]
8002bfe: D5F83802         LDR.W           R0, [R5, #568]
8002c02: 20F00700         BIC.W           R0, R0, #7
8002c06: 40F00200         ORR.W           R0, R0, #2
8002c0a: C5F83802         STR.W           R0, [R5, #568]
8002c0e: 0020             MOVS            R0, #0
8002c10: 04E0             B               0x08002C1C
8002c12:              $C$L4:
8002c12: 2868             LDR             R0, [R5]
8002c14: 62F30200         BFI.W           R0, R2, #0, #3
8002c18: 2860             STR             R0, [R5]
8002c1a: 0920             MOVS            R0, #9
8002c1c:              $C$L5:
8002c1c: 4146             MOV             R1, R8
8002c1e: 0022             MOVS            R2, #0
8002c20: 0A70             STRB            R2, [R1]
8002c22:              $C$L6:
8002c22: BDE8F883         LDMIA.W         R13!, {R3, R4, R5, R6, R7, R8, R9, PC}
8002c26: C046             MOV             R8, R8
8002c28:              $d:
8002c28:              $C$CON1:
8002c28: 5070            .half		 0x7050
8002c2a: F8FF            .half		 0xFFF8
8002c2c:              $C$CON2:
8002c2c: EC3B            .half		 0x3BEC
8002c2e: 0008            .half		 0x0800
8002c30:              $C$CON3:
8002c30: B0FE            .half		 0xFEB0
8002c32: F70F            .half		 0x0FF7

I believe the line w. the CMP, R5, R0 is the comparison that we think should be 28 > 28, and it should be false but instead you're getting the error code.

I would suggest as a next step to step through the code and a) make sure it's the actual code, because it's code that has to be copied from the load address to the run address in RAM before being copied. So there's a chance of a corruption do to a pointer issue or stack underflow issue that may be corrupting the code, and then this would explain the weird behavior. Therefore you should check the disassembly against the values you see in the disassembly in CCS to make sure the opcodes actually match the disassembly of the .out file.
Then, if that is OK, by stepping through the compare to the exit, you can look at the registers and see what values are actually being compared. I think it should be 28 and 28 in R5, R0 respectively but at runtime you'll actually see. If they're vastly different for some reason then we can trace back from there which of the two is wrong.

Best Regards,
Anthony

Hi Tammy,

1) No I used a command line tool - will come back to this, but there should be a screen shot of the command line in the previous post so you can repeat it if needed.

2) Yes, I understand you are executing the F021 API from RAM and you are not trying to program bank 7.  However you are getting a very specific error code that comes only from one test in the API code, and we seem to have ruled out the obvious test which would be 28MHz > 28MHz.   (where the first 28MHz comes from SYSCLK and RWAIT, and the 2nd comes from the OTP setting).     The other path for this error code is through the same comparison but instead of 28MHz calculated by the API using SYSCLK and RWAIT,  if you have bank 7 selected to initialize it would use SYSCLK and *EWAIT* for the comparison instead. 
 I don't think we ever confirmed your value of EWAIT.     But this is why I bring up Bank 7 as a possibility.

Ok so coming back to the first point,  I'm guessing that you'll find there is a problem with the runtime version of the F021 API - maybe it wasn't copied correctly to RAM or maybe it was corrupted.

The DISASM file that I posted came from the Host PC,  There is a command line tool in the <ccsv6>\tools\compiler\<ti-cgt-arm_x.y.z>\bin folder called  'armdis' that I used to generate this.

The disassembly file gives you two things:

  a) a way to check that the RAM contents in the area of the F021 API's run address range match the copy of the code in flash... when you step into the code during the call to the F021 API function.    

    Since somewhere in your code you had to copy from the load address (flash) to the run address (in SRAM) and since SRAM is writeable - it's quite possible that by the time you execute the F021 API  from RAM, some other code has written over it and you're not actually executing the API function that you think you are.

 b) If (a) isn't the case,  at least you can see what registers are being compared and why the decision is made to return the invalid clock error code.   Then knowing the values we can trace back where they came from and that should help us understand what is going wrong.

I happen to think (a) is the most likely because the bootloader's apparently working fine for others.  If it's an issue of not being copied in the first place then this is just a function call that needs to be added.  If it's a corruption issue, then we can zero in on it by putting a watchpoint covering the area of the F021 API in RAM and turning it on after the initial copy.   Whoever then tries to write to the area will trip the watchpoint and you'll find the offending code very quickly.

But if it's not (a) then the information from stepping through and finding out what it's actually comparing will also explain a lot.

Thanks and Best Regards,

Anthony

Hi Anthony. for the "is the comparison that we think should be 28 > 28" in the assembly code -- could the equivalent line in what I saw and copy/pasted for you be

08002982: 45B9 CMP R9, R7

if so, in CCS Registers debugger window. R7 is 0x19 (decimal 25) and R9 is 0x1C (decimal 28).

When I am single stepping after this with debugger it is actually this line:

0800299e: 4871 LDR R0, $C$CON4 (R0 = 0x640)

which jumps to

$C$L3:
080029ae: 2008 MOVS R0, #8
080029b0: E000 B $C$L5

The disassembly of our out file is here:5751.disasm.txt

Hi Anthony. And the screen shot of disassembly text file nest to CCS disassembly window to single step with debugger. It looks the same when I start at the F021 Fapi_initializeFlashBanks assembly code -- but what is it you want me to look for specifically?  

Tammy,

A bit of info on the E bit in the CPSR. It's bit 9 and it controls the 'data endianess' - the endian on loads and stores.

The instruction endianess is controlled by a pin setting (and hardcoded to LE for your RM48).  So instructions won't be interpreted 'backwards' if the E bit is flipped - but some data accesses that are < 32 bits (LDRH, LDR, STRH, STR) would be affected.

This could actually explain why you can seemingly step through the code w. the right inputs but get the wrong result.  Since the opcodes would be unchanged, 32-bit pointers to memory would still be ok, etc.   But it is probably enough of a swap to make the code return an unexpected result, so eager to know about the CPSR E bit state.

Thanks and Best Regards,

Anthony

Hi Anthony,

Where did you look and saw that the endianess was weird?Can you give an example? I did not understand where in the CCS IDE you saw that in the screenshots I gave you? Just so I am on the same page with you thank you.

as you requested:

1. the memory dump at 0x800290C screen shot in CCS:

2. screen shot the value of CPSR when the debugger is at 0x800290C single stepping through code in CCS

3. Screen shot of  disassembly in CCS:

Thank you again

Hi Tammy,

Actually you've captured it in your screenshots above.

Look at the first address for example:

Memory Window         0x47F0E92D

Disassembly Window    0xE92D47F0

Disasm says           0xE92D47F0   (from your post at 4:56 PM yesterday)

Disasm says           0x2DE9F047   (from your post at 5:21 PM yesterday)

So I'm really lost now ;)  Next step is to figure out which one of these three

it should be by checking the ARM instruction set manual ...

Best Regards,

Anthony

Hi Anthony. Yes I saw that -- it is the output from the CCS debugger. As you requested when I singlestep at that point the CPSR changes every few lines (see below). Is there line you want me to singlestep and capture  the CPSR value for?

Hi Anthony. Just to be sure 100% I am uploading again the rezip of the whole project here:  8156.SafetyMCU_Bootloader_Original_FlashIssue.zip

It should just work for you out-of-box on your TI Hercules RM48L952ZWT board (it is the TI bootloader project we downloaded from TI) .You wrote: "Maybe you could watch the flash API code get copied to the SRAM, and see if it's being copied over correctly; but then appears to change later. Or if it's 'reversed' right from the get-go. " How do you want me to do that using CCS?  Thank you again

Tammy,

I did check your code (from your latest zip file) and here is the reason of your problem.

Your application (bootloader) is compiled with optimization (-o3, --opt_for_speed=2)
This is in normally not a problem but the bootloader is based on an old version of Halcogen, and because of that, optimization is causing a problem in system.c

Let me explain.

In system.c, there is a call to void setupFlash(void). This routine is setting up the waitstate for Bank0, Bank1 and Bank7 (EEPROM)

The waitstate register for Bank7 is protected by a key. It is necessary to write 0x05 in this FSM_WR_ENA prior to write the waitstate in EEPROM_CONFIG.
The code is as following:

    /** - Setup flash access wait states for bank 7 */
    FSM_WR_ENA = 0x5;
    EEPROM_CONFIG = 0x00030002;

/* USER CODE BEGIN (7) */
/* USER CODE END */

    /** - Disable write access to flash state machine registers */
    FSM_WR_ENA = 0xA;

Because of optimization and also because of the definition of FSM_WR_ENA, the first write is not performed. So later on, the Waitstate are not set correctly.

In the bootloader code, when the test is performed to check the running speed versus the Flash configuration, it is failing for EEPROM Bank7.

The quick way to fix this problem is to edit the property of system.c and specify no optimization. The rest of the project will still have optimization.

On my side, I'm working on a revise version of the bootloader based on the latest release of Halcogen. For information, with release 04.05.00 the FSM_WR_ENA register it defined as volatile. With this definition, with or without optimization, the code will stay and work as expected.

Now there is another problem in your bootloader. When the code is finally downloaded and flashed in the device, a specific location is written with a magic number to specify to the bootloader on a subsequent boot that there is no need to download a new code anymore (unless the GIOA7 key is pressed)

By default, the location is defined in bl_main.c as:

uint32_t g_ulUpdateStatusAddr = 0x07FC0;

This is the last 4 words of sector0 Bank0.
This is no more possible with the addition of the SD card support. The bootloader code is bigger and this location is already used by your code.
The solution is to move this magic number to the end of sector 1 of Bank0 as following:

uint32_t g_ulUpdateStatusAddr = 0x0FFC0;             //was 0x07FC0

If your bootloader is growing (check the map file) than at one point it will be necessary to move this Magic number to the next sector.

Please have a try and let me know your result.