• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 30 subscribers
  • Views 534 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Hardware pin assignments for DMA Request sources

Steve Woelfle
Prodigy 40 points

Where can I find a clear, concise mapping of DMA Request sources to hardware pin assignments? Specifically,  what pins do the DMA Request sources listed in SPNS191B table 6-32 map to?

  • 0
    TI__Guru 59540 points
    Hello Steve,

    The DMA request lines are not connected to physical pins. They are connected internally to the IP/modules listed in the table you reference. The DMA HW triggering functionality for each respective module is described within the chapters for the specific IP. As an example, you will see in the DCAN chapter that it is described how to enable DMA HW triggering when a write to the IF3 register occurs (indication that a message was received).
  • 0 in reply to Chuck Davenport
    Prodigy 40 points
    The situation I'm trying to resolve is to use DMA to transfer a block of data from external memory on the EMIF port to internal memory based on condition of an external DATA_RDY signal input as a trigger. If all the DMA requests are from internal HW triggers, how would you suggest I could accomplish this?
  • 0 in reply to Steve Woelfle
    TI__Guru 59540 points
    Hi Steve,

    Unfortunately, there isn't a HW request line associated with the EMIF or even one tied to GPIO. One way to possible get around this is to use a interrupt capable GPIO and whithin the interrupt, trigger a SW request for the DMA transfer from the EMIF address range to the internal address range. This isn't ideal, but still can save the CPU time to perform the transfer.