PMU Initialization Driver

Ryan Smoots

Other Parts Discussed in Thread: RM48L952, HALCOGEN

I am using the RM48L952.

Upon reviewing the HALCoGen PMU initialization driver I noticed that the Count Enable Set Register (PMCNTENSET) is written with 0x11 for each of the three counters. PMCNTENSET[0] is the counter 0 enable bit. However, PMCNTENSET[4] is a reserved bit. Why is it being written? See the register definition here:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0363g/Bgbejcgj.html

And the function here:

;-------------------------------------------------------------------------------
; Initialize Pmu
; Note: It will reset all counters
; SourceId : PMU_SourceId_001
; DesignId : PMU_DesignId_001
; Requirements : HL_SR484

    export     _pmuInit_
    

_pmuInit_

        stmfd sp!, {r0}
        ; set control register
        mrc   p15, #0, r0, c9, c12, #0
        orr   r0,  r0, #(1 << 4) + 6 + 1
        mcr   p15, #0, r0, c9, c12, #0
        ; clear flags
        mov   r0,  #0
        sub   r0,  r0,  #1
        mcr   p15, #0, r0, c9, c12, #3
        ; select counter 0 event
        mcr   p15, #0, r0, c9, c12, #5 ; select counter
        mov   r0,  #0x11
        mcr   p15, #0, r0, c9, c13, #1 ; select event
        ; select counter 1 event
        mov   r0,  #1
        mcr   p15, #0, r0, c9, c12, #5 ; select counter
        mov   r0,  #0x11
        mcr   p15, #0, r0, c9, c13, #1 ; select event
        ; select counter 2 event
        mov   r0,  #2
        mcr   p15, #0, r0, c9, c12, #5 ; select counter
        mov   r0,  #0x11
        mcr   p15, #0, r0, c9, c13, #1 ; select event
        ldmfd sp!, {r0}
        bx    lr

over 10 years ago

0 Chuck Davenport over 10 years ago

TI__Guru 59540 points

Hello Ryan,

I am forwarding your question to our Halcogen team as they are better suited to answer questions regarding the code generated by Halcogen. They should get back with you soon.

0 Charles Tsai over 10 years ago in reply to Chuck Davenport

TI__Guru**** 191886 points

Hi Ryan,

I think it is writing 0x11 to the Event Type Selection Register since the coprocessor instruction used is mcr p15, #0, r0, c9, c13, #1. 0x11 will select Cycle count as the event for the counters. Please refer to the Table 6-1 Event bus interface bit function in the Cortex-R4/5 TRM for each event reference number.

0 Ryan Smoots over 10 years ago in reply to Charles Tsai

Intellectual 260 points

Thanks for your prompt reply, Charles.

The driver writes 0x11 to the Count Enable Set Register, not the Event Type Selection Register. Secondly, I searched the Cortex-R4 TRM for "Event Type Selection Register" to no avail. Table 6-1 is the TCRAM Module Control and Status Register Map, not event bus control.

Again, please see the ARM documentation for this register here:
infocenter.arm.com/.../index.jsp

Those reserved bits [30:3], are they implemented as documented somewhere in the TRM? If so, please point me to that.

Thanks,
Ryan

0 Charles Tsai over 10 years ago in reply to Ryan Smoots

TI__Guru**** 191886 points

Hi Ryan,

If you look at the code it is writing to c9, c13, 1, not c9, c12, 1 which is is the PMCNTENSET register.

       mcr   p15, #0, r0, c9, c12, #5 ; select counter

       mov   r0, #0x11

       mcr   p15, #0, r0, c9, c13, #1 ; select event

For the event bus table please first download the cortexr4 r1p4 TRM at the below link. Table 6-1 is in page 158.

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0363g/DDI0363G_cortex_r4_r1p4_trm.pdf

0 Charles Tsai over 10 years ago in reply to Charles Tsai

TI__Guru**** 191886 points

Ryan,
Also the Event Type Selection Register is described in section 6.3.8 or page 170.

0 Ryan Smoots over 10 years ago in reply to Charles Tsai

Intellectual 260 points

Ahah, I misread the coprocessor number. Thank you.

0 Ryan Smoots over 10 years ago in reply to Ryan Smoots

Intellectual 260 points

Hello again Charles,

Okay, this time I really do think that I found a bug in this driver.

In _pmuInit_ see the following instructions which are supposed to select counter 0.

        ; select counter 0 event
        mcr   p15, #0, r0, c9, c12, #5 ; select counter
        mov   r0,  #0x11
        mcr   p15, #0, r0, c9, c13, #1 ; select event

Note that r0, the register that is stored into the PMSELR, has a value of 0 - 1 = 0xFFFFFFFF from the flag clearing instructions above this code excerpt.

Stepping through the code and viewing the PMSELR[4:0], it is 0x3 which indicates that both counters 1 and 2 are selected.

First of all, shouldn't r0 get zeroed before being used to store into PMSELR so as to select counter 0?

Secondly, isn't this an undefined state to have multiple counters selected? What will happen if say the PMXEVTYPER is written? Will it write PMXEVTYPER1 or PMXEVTYPER2?

Thanks,

Ryan

0 Charles Tsai over 10 years ago in reply to Ryan Smoots

TI__Guru**** 191886 points

Hi Ryan,

I agree with your analysis. Could you tell me which HalCoGen version you are using? I just used HalCoGen version 04.05.00 and it has the r0 cleared to 0 before selecting the first counter. I will suggest that you move to the latest version of HalCoGen. Please let me know if you are still seeing the mistake in the latest HalCoGen version.

_pmuInit_

        stmfd sp!, {r0}
        ; set control register
        mrc   p15, #0, r0, c9, c12, #0
        orr   r0,  r0, #(1 << 4) + 6 + 1
        mcr   p15, #0, r0, c9, c12, #0
        ; clear flags
        mov   r0,  #0
        sub   r0,  r0,  #1
        mcr   p15, #0, r0, c9, c12, #3
        ; select counter 0 event
        mov   r0,  #0
        mcr   p15, #0, r0, c9, c12, #5 ; select counter
        mov   r0,  #0x11
        mcr   p15, #0, r0, c9, c13, #1 ; select event
        ; select counter 1 event
        mov   r0,  #1
        mcr   p15, #0, r0, c9, c12, #5 ; select counter
        mov   r0,  #0x11
        mcr   p15, #0, r0, c9, c13, #1 ; select event
        ; select counter 2 event
        mov   r0,  #2
        mcr   p15, #0, r0, c9, c12, #5 ; select counter
        mov   r0,  #0x11
        mcr   p15, #0, r0, c9, c13, #1 ; select event
        ldmfd sp!, {r0}
        bx    lr

    .endasmfunc

0 Ryan Smoots over 10 years ago in reply to Charles Tsai

Intellectual 260 points

I am using HALCoGen 04.02.00. The bug is fixed in 04.05.00. Thanks again.

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PMU Initialization Driver