Usage of EMIF from different RTOS tasks

Thomas Weber

Hello,

in a project we want to use SRAM and UART on different EMIF Chip Select.

Is it possible to use both ports from different tasks (with different priorities) and without preventing task switches (use of CRITICAL_SECTION)?

Best regards,

Thomas

over 10 years ago

0 KARTHIKEYAN RAJAMANICKAM over 10 years ago

TI__Genius 11645 points

Thomas,

Are you asking if you can have SDRAM and another Asynch Ram connected to one of the CS working together ?

0 Thomas Weber over 10 years ago in reply to KARTHIKEYAN RAJAMANICKAM

Intellectual 680 points

Hello Karthik,

thanks for paying attention to my question.

The RAM and the parallel UART (TLC16C2550) are connected to different CS wires.

My question is related to a task switch between EMIF communication.

Example:
task1 reads from RAM
task2 writes to UART

Is this a problem for EMIF if during data transfer a task switch occurs?

Regards,
Thomas

0 Anthony F. Seely over 10 years ago in reply to Thomas Weber

TI__Guru 69070 points

Thomas,
No (EDIT: No Problem for the EMIF) - the EMIF can switch between async-async and async-sdram chip selects automatically.
Also see the "TA" field of the Async control registers (CE2CFG-CE5CFG) - it allows some additional time when switching between reads & writes as well as async and sync - this is useful if one of your external devices takes a long time to 'get off' the bus after being deselected.

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Usage of EMIF from different RTOS tasks