TMS570LS20216ASPGE, Halcogen, and ECC Ram Enable

Chad Zalkin

Other Parts Discussed in Thread: HALCOGEN

I am using a TMS570LS20216ASPGE, and attempting to enable and verify the ECC RAM and Flash. I followed the notes in spna126 and other posts on the forum, and I am unable to detect single bit flips in RAM. I noticed that the sample projects that have been posted have additional steps in the halcogen generated code, including ecc self test and enabling of other options. Further, the 20216SPGE Halcogen project does not have "RAM ECC Enable" as an option on the RAM page. Other 570 chips have this option and generate code to manage the ECC.

Is there a setting I am missing, or is my chip configured differently? Can I generate a sys_startup.c for another chip and use that code in my project?

over 10 years ago

0 KARTHIKEYAN RAJAMANICKAM over 10 years ago

TI__Genius 11645 points

Hello Chad,

Can you pls check if you have the RAMTHRESHOLD set to a non-zero value ?

In the meanwhile I will check with the Halcogen team.

0 Chad Zalkin over 10 years ago in reply to KARTHIKEYAN RAJAMANICKAM

Prodigy 50 points

KARTHIKEYAN RAJAMANICKAM said:
Hello Chad,

Can you pls check if you have the RAMTHRESHOLD set to a non-zero value ?

I have tried varying values of RAMTHRESHOLD, and it does not seem to have an effect on my test case.

0 KARTHIKEYAN RAJAMANICKAM over 10 years ago in reply to Chad Zalkin

TI__Genius 11645 points

If you could share your code, I can take a look at it.

0 Chad Zalkin over 10 years ago in reply to KARTHIKEYAN RAJAMANICKAM

Prodigy 50 points

I've attached the relevant parts of my code. In ecc_c_functions.c, I have generated two test cases, and both test cases return 0 ecc errors. These test cases are taken and modified from other posts I have found on this forum and the various documentation sources.

7875.eccProblem.tar.gz

0 KARTHIKEYAN RAJAMANICKAM over 10 years ago in reply to Chad Zalkin

TI__Genius 11645 points

Chad,

Got your files, pls give me sometime so that I can debug this and let you know.

0 KARTHIKEYAN RAJAMANICKAM over 10 years ago in reply to KARTHIKEYAN RAJAMANICKAM

TI__Genius 11645 points

Chad,

I just got to this. Can you pls help me with the complete project instead ?

Since I'm using the latest halcogen version and I'm not sure of the attached with few headers missing/different naming conventions I'm not able to proceed with the build.

0 Chad Zalkin over 10 years ago in reply to KARTHIKEYAN RAJAMANICKAM

Prodigy 50 points

7853.eccTest.tar.gz

I was able to get an ECC test working with a small test case project that I've attached here. When I created the test application, I was unable to reproduce the issue that I am having in our application. Comparing the differences led me to notice that any optimization other than --opt-level=off causes the test to fail to run successfully. We are not using code composer to generate our build, and were incorrectly specifying --opt-level=0 when attempting to turn off optimization. This allows me to verify the ECC in the application, but requires that I disable optimization, which is not ideal. I suppose that this is to be expected because the test is poking registers and doing idempotent reads.

Thanks for the help.

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TMS570LS20216ASPGE, Halcogen, and ECC Ram Enable