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TM4C123BH6ZRBI7 Internal Flash Erase Blocking Question

Dennis Nguyen
Expert 1690 points
Other Parts Discussed in Thread: TM4C123BH6ZRB

Hi,

I am erasing 1 1KB flash block and it did complete the erasing a little over 8ms as the datasheet stated. The 1KB block internal flash was erased. My question is writing the HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE; HWREG doesn't return to the firmware until 8ms later.

#define HWREG(x)  (*((volatile uint32_t *)(x)))

The firmware has to kick the watchdog every 3ms and this HWREG(FLASH_FMC) is blocking for over 8ms.

I reviewed Tiva TM4C123BH6ZRB Microcontroller DATA SHEET and tried a couple options for FLASH_FCMISC but the result is the same. Here are my register settings:

CPU_RegisterWrite( FLASH_FCMISC, (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC | FLASH_FCMISC_ERMISC) );

CPU_RegisterWrite( FLASH_FMA, addr_ );

CPU_RegisterWrite( FLASH_FMC, (FLASH_FMC_WRKEY | FLASH_FMC_ERASE) );

My question is does this silicon actually blocks the erase function until it complete or I am missing something in the register configuration? My ultimate goal is sending the erase request and check the complete status may be once every ms or interrupt. Since I can poll FLASH_FMC, I assume that the erase function is non-blocking but it is blocking from my firmware point of view.

Please comment. Thanks.

Dennis

  • 0
    Expert 1690 points
    Also on top of the described description, my TM4C123BH6ZRBI7 is a slave SSI to another microcontroller. There are symptoms of the SSI Slave DMA is locked up and never recover correctly with the master SSI after internal flash performing 1KB erasing. I guess the firmware can do a DMA reset but I think it shouldn't have to. Please comment.
  • 0
    TI__Guru**** 244400 points
    Hello Dennis,

    The Flash Program or Erase will stall the CPU bus till the operation is not complete. This is mentioned in the data sheet as well.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Expert 1690 points

    Thanks, Amit. I thought there is a chance that you come back and tell us we did something wrong and how to fix the configuration. This is not the case.

  • 0 in reply to Dennis Nguyen
    TI__Guru**** 244400 points
    Hello Dennis,

    To see why the SSI DMA is locked up, you would need to share the configuration and use code for the SSI and DMA.

    Regards
    Amit
  • 0
    Guru 92251 points

    Dennis Nguyen - Flex said:
    My question is does this silicon actually blocks the erase function until it complete or I am missing something in the register configuration? My ultimate goal is sending the erase request and check the complete status may be once every ms or interrupt. Since I can poll FLASH_FMC, I assume that the erase function is non-blocking but it is blocking from my firmware point of view.

    Section 8.2.3.7 Flash Memory Programming of the datasheet says:
    During a Flash memory operation (write, page erase, or mass erase) access to the Flash memory is inhibited. As a result, instruction and literal fetches are held off until the Flash memory operation is complete. If instruction execution is required during a Flash memory operation, the code that is executing must be placed in SRAM and executed from there while the flash operation is in progress.
    Have you tried running the code from SRAM to start an erase, and then poll for the flash erase to complete?

  • 0 in reply to Dennis Nguyen
    Guru 92251 points

    Dennis Nguyen - Flex said:
    . There are symptoms of the SSI Slave DMA is locked up and never recover correctly with the master SSI after internal flash performing 1KB erasing.

    The datasheet mentions that "µDMA controller access is subordinate to core access".

    If the CPU is running from flash during an erase, the CPU core will stall. The CPU core stalling may then cause the µDMA controller access to also stall.

    Perhaps if the CPU core is running code from SRAM during the flash erase, the SSI Slave DMA may then be able to continue.

    [I haven't attempted to test this myself]

  • 0 in reply to Chester Gillon
    TI__Guru**** 244400 points
    Hello Chester

    Not for the DMA. The DMA is accessing the SRAM which will be allowed by the bus core.

    Regards
    Amit