Expand ECC to EMIF SDRAM memory

Hi Antonio,

your post is two years old, but now there is a solution in a different way.

There are SDRAM components with on-chip ECC from the manufacturer Intelligent Memory   www.intelligentmemory.com/.../

Part# IME5116SDBETG-75I has 512Mb in a x16 organization in TSOP54 or BGA54 package. There are also parts with 32 bit wide interface in TSOP86 or BGA90

Optionally (these are not shown on website), there are also extra-robust cell-twinned 256Mb ECC product. In x16 the part# is IMX2516SDBETG-75I   You can request these by contacting the manufacturer or their distributors.

These ECC SDRAM chips detect and correct bit-errors on their own and are fully compatible to conventional SDRAMs from other makers. There are no changes or adaptions required to the hardware or software to use them. Simply put as a replacement for the conventional DRAM them in and experiment (for example by applying strong heat or radiation) to get them to fail.

There is no communication of corrected errors to the CPU though, as otherwise the parts would no longer be compatible to standard SDRAMs.

However, if you understand the physics behind DRAM-errors and their probability&frequence, you will notice that such DRAM-integrated ECC will result in failure free operation for years! What would it help if the CPU knew that a bit-flip was corrected? At the end of the day you want the system to continue running, being "available". A simle comparison: A home-PC or laptop needs to be rebooted once a week, while a server with ECC runs for years without ever being rebooted. Do you need to know how often the server corrected a bit-flip? Not really.

Most bit-errors in DRAMs appear due to degradation, leakages only showing with depending on specific bit-patterns or they come from VRT-effects. All of these are related to insufficiencies of the very little capacitors used to store a minimal charge deciding about a databit being zero or one. Utilizing a DRAM with integrated ECC that is executed by and inside the DRAM will provide a major improvement of the application availability and stability. The risk of transmission-errors between RAM and CPU is close to zero compared to bit-flips occuring in the memory-array of the DRAM itself.

Double-bit error detection and signalling to the CPU would be nice, but statistically a double-bit error has a probability that is lower than a permanent fail or complete row/column fail of the DRAM. Triple or more bit errors could also not be detected. This being said a "double-bit error detection" also looks not very valuable, as it is less important than some functional-safety-hardware which watches if the complete system is still running.

The "extra robust cell twinned" 256Mb ECC SDRAM devices basically are the same 512Mb ECC SDRAMs, but during production the internal DRAM-logic is trimmed to use two memory-cells in parallel for each bit. Thus the capacity goes down to 256Mb, while the robustness to all the potential root-causes for single-bit-errors increases exponentially. The twinned memory-cells hold much higher charge for each databit, which increases the data-retention. Even if one of the two twinned cells has an retention-related issue, the two twinned cells together still result in a valid databit. And even in the rare case that the twinned-cell databit became incorrect, there is still the integrated ECC that corrects it.

Regards,

Thorsten