Back tracking issue:
https://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/p/417592/1490210#1490210
https://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/t/409303
The Stellaris group overrides of (opts.h) -- (PBUF_POOL_BUFFSIZE) in (lwipopts.h) migrated into Tivaware has compatibility issues with DMA descriptor PBUF.
Likewise when (tcp_in.c) out of sequence frames are queued in SRAM PBUF's they randomly cause heap memory to slowly collapse with (opt.h) defaults OOSEQ_MAX_PBUF == 0, OOSEQ_MAX_BYTES == 0. More of that below posting.
Random peripheral bus faults are very difficult to track down the what or why of them occurring and seemingly can stem from more than one origin.
Especially true given the complexity of Adam Dunkels LWIP heap memory management techniques. Tivaware includes the third party LWIP to take advantage of the advanced TM4C1294 EMAC designed with state of the art DMA RX/TX descriptors.
The lesson learned, do not accept vendor prepackaged configurations as being foolproof, do that yourself and test the C code perpetually.
http://lwip.wikia.com/wiki/Tuning_TCP