Hi,
How cab I make the SSI module sends the Least significant bit first?
I couldn't find it in the TivaWare™ Peripheral Driver Library.
Thanks.
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Hi,
How cab I make the SSI module sends the Least significant bit first?
I couldn't find it in the TivaWare™ Peripheral Driver Library.
Thanks.
Moha Deeb1 said:How cab I make the SSI module sends the Least significant bit first?
Would that (even) be wise? Do you know of a (real) SPI device which "welcomes" LSbit first?
From the MCU manual (required reading - at least the peripherals you employ):
Again - beware of that which you (appear) to seek. If you (really) wish to transfer lsb first you must "reverse the bit order" prior to routing that data into the SSI module.
Hi cb1_mobile,
Thanks for the reply.
I am using a DDS chip from a certain manufacturer, there is a frequency control register which should be written to LSB first.
currently we reverse the order of bits in code, but I thought using the peripheral H/W to saves some cycles.
Thanks.
Moha Deeb1 said:...using a DDS chip... from another... there is a frequency control register which should be written...LSB first.
That seems strange - a "real" vendor should have anticipated SPI's, "bit order" - and designed their register access in support. The high-speed & combined data/clock output of SPI seems obvious - hard to explain how "another" missed...
Might you "link" to the DDS data (don't provide vendor's name) & I'll have staff check to see if we agree w/your "SPI bit order" interpretation?
Assuming what you state proves correct - how clever is your, "reverse of the bit order" code?
cb1_mobile said:That seems strange - a "real" vendor should have anticipated SPI's, "bit order"
Staff/I have checked our most recent DDS device, "AD9858" 1GHz clocked & able to generate a: "frequency-agile, analog output, sine wave at up to 400MHz." (note: cb1 expects to be featured by this vendor w/in coming months...)
Pertinent info - directly from that device's data sheet "agrees" with our (earlier) supposition: (i.e. real maker would not "blow" the SPI spec)
You will (readily) note that - as we surmised - MSB "leads" the bit parade! (nothing new there...)
And (just prior) to this (detailed, MSB first) chart appeared:
Note that last sentence - this particular device is so well thought/conceived that even the bit order - may be changed. (and for both phases!)
We remain in doubt as to any "real device" mandating a lsb first order via SPI... (perhaps you/group "misread")
Hi cb1_mobile,
I didn't mention it's an SPI, maybe I should've emphasized more on that, sorry.
it's a synchronous serial, that's why we are using SSI module to interface it.
here is the link.
Thanks.
May we note that "bit order reversal" has appeared (at least) three times (earlier) in this thread. The bit order output of your MCUs has been "copy-pasted" to further drive/justify that point... (it would appear that point "had" been well covered)
Hi cb1_mobile,
Thanks for the code review in advance,
uint8_t ReverseByte(uint8_t inByte) { uint8_t outByte = 0, counter = 0; for (; counter < 8; counter++) { if (((inByte >> counter) & 0x01) == 1) { outByte |= 1; } if (counter < 7) { outByte <<= 1; } } return outByte; }
Hi,
There is also the possibility to do it with .asm language instruction rbit. Depends on your tools - CCS implements several intrinsic functions for that: __rbit. See spnu151i.pdf (ARM Optimizing Compiler v5.1 User's Manual,pg 103).