• State
  • Locked Locked
  • Replies 6 replies
  • Subscribers 32 subscribers
  • Views 845 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Uart0 tX0 intr on tm4c1230 not working

rali
Prodigy 20 points

Hi,

I am new to the Tiva micro and need some help.

I am trying to get an interrupt at the end of each byte transmitted on TX0 or at the end of the packet;

I get no interrupt if I send 1 byte, or 3 bytes. If I send 22 bytes, I get an interrupt at around byte # 16.

I used  i = UARTTxIntModeGet(UART0_INDEX);   to verify that UART_TXINT_MODE_EOT was active.

I am using the following code, please let me know where I am making the error

Thanks for your help

Rich


  //init uart0
  ROM_IntPrioritySet(INT_UART0, UART0_INTERRUPT_LEVEL);
  ROM_GPIOPinConfigure(GPIO_PA0_U0RX);
  ROM_GPIOPinConfigure(GPIO_PA1_U0TX);
  ROM_GPIOPinTypeUART(PIN_U0RX_PORT, PIN_U0RX_PIN);
  ROM_GPIODirModeSet(PIN_U0TX_PORT, PIN_U0TX_PIN, GPIO_DIR_MODE_HW);
  ROM_GPIOPadConfigSet(PIN_U0TX_PORT, PIN_U0TX_PIN, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
  i_set_interrupt(INT_UART0, SerialUART0IntHandler, 0);
  SerialSetURT(PANEL_KP_UART_INDEX, BAUDRATE_UART0, UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_EVEN,
               SERIAL_FLOW_CONTROL_NONE, false, UART_FIFO_TX1_8, UART_FIFO_RX1_8); //true==disable FIFO
  //switch from FIFO intr to EOT intr which allows for single byte intr
  UARTTxIntModeSet(PANEL_KP_UART_INDEX, UART_TXINT_MODE_EOT);
  ClearUart0Buf(PANEL_KP_UART_INDEX, CLR_FULL_BUF);
//  ROM_UARTIntDisable(g_ulUARTBase[PANEL_KP_UART_INDEX], (UART_INT_RX | UART_INT_RT));
  ROM_UARTIntClear(g_ulUARTBase[PANEL_KP_UART_INDEX], 0xFFFFFFFF);

  • 0
    TI__Guru**** 244400 points
    Hello Rali,

    What is the value of the EOT bit in the UARTCTL register and can you also check if the FIFO is enabled?

    The FIFO is enabled in my opinion and the EOT bit is cleared. In this case the TX interrupt will be asserted only when the UARTTXFLS value is crossed.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Guru 47900 points

    Always love it when posters' proclaim, "XYZ of my MCU NOT Working!"

    And - driving toward infinity - it is posters' set-up/code which proves, "Not Working!" There is a difference - devil in such details...

  • 0
    Guru 26105 points

    Hi,

    Please never ever (to use some words not agreed by cb1..) forget that UARTEnable() function silently enable also the FIFO. In such case the correct code sequence should be:

    UARTEnable();

    UARTFIFODisable();

    If you want an interrupt after each byte sent, then use interrupt on TX. In such case to start sending, first byte should be manually sent to UART data register and from there all is automatic (adjust your code accordingly...).

    Not checked your code, but at first sight, seems unusual configuration - please look at some examples provided by TI.

  • 0 in reply to Petrei
    Guru 47900 points

    Let the record show that poster "Petrei" is granted "special exemption" from the "banned/beware word listing" previously appearing (here) as public service...

  • 0
    Prodigy 20 points
    Hi Guys,
    The title of this post was definitely bad, stand corrected.
    Thanks for your input
  • 0 in reply to rali
    TI__Guru**** 244400 points
    Hello Rali

    Did you check the comments from Petrei. If the FIFO is enabled then the TX threshold has to cross the set FIFO level. Also when you set the FIFO threshold to 1/8 of the FIFO (which is 2 bytes), writing 3 bytes may not be sufficient as the transmission of the byte has already started so the FIFO would only be at 2. You may have to write 4 bytes to get the TX interrupt.

    Regards
    Amit