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enet_lwip and UART problems

Other Parts Discussed in Thread: EK-TM4C1294XL, TM4C1294NCPDT

Hi there fellows, I'm writting today because I have a problem a running a local webpage, based on the enet_lwip project, and the UART 7 port. The fact is that I'm measuring some variables with the TivaC and sending  SMS messages thorugh a SIM800L modem. The comunnication between them is made thorugh the UART7 ports: PORTC4 -> RX(7), PORTC5 -> TX(7). The rare thing is that the SMS is send succesfully but after that the webpage stops working. I have: verified that the SMS code doesn't disable any ethernet interruption and changed the UART port, but the problem still goes on. 

Any idea?

Thanks in advanced, Regards

MARTIN C!

  • Hello Martin,

    1. When the web page stops working, does Wireshark show any message being sent by the hosted page to the TM4C device?
    2. If you replace the SIM800L by a dummy write on UART7 ports does the issue still occur.

    Do understand that we do not have your setup and the only thing we can do is to send a dummy UART7 TX out and a dummy UART7 RX in to emulate the SIM800L modem.

    Regards
    Amit
  • Hi Martin,

    I had an issue with LWIP (enet_lwip) where after some web pages were loaded, the LWIP (with an incoming page request) didn't have enough memory to store the connection state. The client browser went into a connection loss event. To determine if this is your situation, in the http.c file look for function http_accept() and locate the following

      /* Allocate memory for the structure that holds the state of the
         connection - initialized by that function. */
      hs = http_state_alloc();
      if (hs == NULL) {
        LWIP_DEBUGF(HTTPD_DEBUG, ("http_accept: Out of memory, RST\n"));
        return ERR_MEM;
      }
    

    On the line "return ERR_MEM" place a breakpoint. If you hit that breakpoint, then your having a memory starvation situation like I had.

    I fixed the problem by enabling these two defines in the lwipopts.h file and used my own memory pools.

    #define MEM_USE_POOLS                                 1
    #define MEMP_USE_CUSTOM_POOLS           1

    Hope this helps,

    Alan

  • Hi Alan,

    Can you post the custom pools (lwippools.h) you created for use with LWIP.  We struggled to get the proper syntax (below) for each independant pool (macro) and instead bumped the HEAP size up to 32kb in lwipopts.h

    * To let mem_malloc() use pools (prevents fragmentation and is much faster than a heap but might waste some memory), define MEM_USE_POOLS to 1, define MEMP_USE_CUSTOM_POOLS to 1 and create a file "lwippools.h" that includes a list of pools like this (more pools can be added between _START and _END):

    Sample (lwippools.h):

    #if MEMP_USE_CUSTOM_POOLS
    
    #define LWIP_MALLOC_MEMPOOL_START
    #define LWIP_MALLOC_MEMPOOL (PBUF, MEMP_NUM_PBUF, 0, "PBUF_REF/ROM")
    #define LWIP_MALLOC_MEMPOOL (RD_PBUF_POOL, PBUF_POOL_SIZE, 512, "PBUF_POOL_1")
    #define LWIP_MALLOC_MEMPOOL (RD_PBUF_POOL, PBUF_POOL_SIZE, 600, "PBUF_POOL_2")
    #define LWIP_MALLOC_MEMPOOL_END
    
    #endif

  • Hi BP101,
    I ended up with the following for my memory pools. I set mine to provide available memory to all of the LWIP code requesting memory. My system is only using 7 web pages with each page requesting pbuf's for files containing CSS, javascript, two images (max), and the favicon which are all small in size. Also the lwippools.h file needs to be in the same directory as your lwipopts.h file.


    /* @file lwippools.h
    * Define three pools with sizes 256, 512, and 1512 bytes */
    LWIP_MALLOC_MEMPOOL_START
    LWIP_MALLOC_MEMPOOL(50, 256)
    LWIP_MALLOC_MEMPOOL(50, 512)
    LWIP_MALLOC_MEMPOOL(10, 1512)
    LWIP_MALLOC_MEMPOOL_END
  • Hi BocaDev,

    With the standard 32k heap it starts at 9386k grows 12k and upward after many hours of operation. Only a few KB ever get returned to the heap and it never compresses once it hits a peak it grows even more. So (mem_free) is not doing a very good job at heap management or it getting so highly fragmented with broken chains TCP just crashes at some point many days out.

    Tried those similar above even adding (#defines) on  each line but get an incompatible redefinition of macro (lwip_malloc_mempool) for the 2nd/3rd pools and (memp_std.c/h) still refuses to build with out errors.  Most the errors indicate the default (memp_pbuf_pool) has already been declared in the current scope even after setting custom/use pools  = 1.  LWIP v.1.4.1

    The default macro (lwip_pbuf_mempool) is some how bound to (mem_pbuf_pool) which uses type (PBUF_RAM) stored in the heap configured for the DMA descriptors by invoking lwip Pbuf allocator in (tiva-tm4c129.c). There must be more to the LWIP configuration settings to use custom pools?

    The default (pbuf_pool) macro refuses to use the new custom memory pools:

    LWIP_PBUF_MEMPOOL(PBUF_POOL, PBUF_POOL_SIZE,    PBUF_POOL_BUFSIZE,     "PBUF_POOL")

  • Hi fellows, thank at all for your participation, I solved my problem. I think I was sending data by the UART in a not aproppiate way, it seems that this make the webpage stops woking. So I used UART2, and at the time of sending the SMS I execute the function: UARTStdioConfig(2, 115200, g_ui32SysClock); It allows me to send data using the function UARTprintf("data"); The advantage of the named function is that it allows to send any kind of string. Finally when the message is sent I execute: UARTStdioConfig(0, 115200, g_ui32SysClock); restoring to the original enet_lwip.c conditions.

    Thanks at all, Regards

    MARTIN C!
  • Hi Martin,

    >The communication between them is made through the UART7 ports: PORTC4 -> RX(7), PORTC5 -> TX(7).

    Makes no sense at all what you described above since UART2 uses different GPIO pins than the ones you stated above. How is the modem working at all using the same GPIO pins?

    Perhaps you physically moved the modem to completely different GPIO pins on the X11 header? If not mistaken last I loaded (enet_lwip) UART0 uses GPIO A0/A1 and is the virtual CDM serial COM port for ICDI USB with a terminal emulator such as Putty. Otherwise if JP4/5 if moved into vertical position (1-3,2-4) UART2 of TM4C1294 is then the virtual COM port visible on ICDI USB.

    Wouldn't you agree It really shouldn't matter to the web page what UART is being asserted as long as the UART FIFO can accept data and the GPIO pins physically connect to the modem?

    From what you described fixed the problem it appears the modem was never on UIART7 to begin with.

  • Thanks for your time BP101, perhaps I don't remarked that the UART7 is not used anymore, I have cahnged it for the UART2: PORTA6 -> RX(2), PORTA7 -> TX(2) in order to use the function UartPrintf(); (function only available to the physic UART2 ports) that's why i said that perhaps I was sending bad data for the UART7.

    Thanks for your time, Regards

    MARTIN C!

  • Yes you did state UART7 not used anymore. That explanation makes no sense why it now works as it should have been working ok with UART7.

    Switching the modem to UART2 Port A6,A7 should not have made any difference if UART7 was actually being configured.

    Port C  due to the JTAG pins C0-C3 are all locked GPIO pins, seemingly GPIO port C4, C5 need be unlocked using mask key code ( |= 0x30). 

    Perhaps you did not unlock the GPIO port C prior to configuring it as UART7? 

  • Hi Martin

    Ok now understand you also discovered Tivaware (UARTStdioConfig) is not programmed for access to UART7. We, you and the world might expect UART7 for use with the EK-TM4C1294XL or TM4C1294NCPDT.

    Typically the Tivaware code should inform us UART7 invalid by error in that SANITY test during the project build! I tend to assume anyone who writes code to restrict peripheral use might include a Sanity test.   

    Good find Martin:

        //
        // Check the arguments.
        //
        ASSERT((ui32PortNum == 0) || (ui32PortNum == 1) ||
               (ui32PortNum == 2));
    

  • BP101 said:

    Port C  due to the JTAG pins C0-C3 are all locked GPIO pins, seemingly GPIO port C4, C5 need be unlocked using mask key code ( |= 0x30). 

    Perhaps you did not unlock the GPIO port C prior to configuring it as UART7? 

    *** ***

    My friend - Port "C" GPIO pins outside of PC0-PC3 require NO SUCH Unlocking!   Here - the MCU manual details:

    Port "A" comes closest to your "seemingly" - but PA6 & PA7 escape - thus NO Port requires a complete Unlock!  We've (long) used "upper nibble" of Port C - never unlocking!

    Devil in such detail - MCU manual provides much...

  • >seemingly GPIO port C4, C5 

    Did use the word seemingly. Albeit long ago CB1 (seemingly) agreed port C unlock (may) be needed for COMP0(C0-/C1-) input assigned GPIO pins C4,C7. To answer BP101 post "Why PinMux tool can not program comparator pins?"

     Tiva Pinmux Tool output file wrote unlock C code for GPIO port C pins C4, C7. That unlock code led to belief the (entire) GPIO C port was indeed locked and Table 9-1 was incorrect. Appears was not alone in that belief to unlock the upper nibble GPIO port C pin [4:7].

    However the Tivaware UARTStdioConfig Sanity ASSERT testing UART0-2 should have produced CCS compiler warnings in the Problems tab.

    Why CCS missing warning lead to this post is interesting yet it revealed other Silent forum posters LWIP1.4.1 confirmed heap issues in memory pool. That is not good for yet again Silent Exosite IOT users that remain in time bomb payload crash out weeks or months online.

     

  • BP101 said:
    Albeit long ago CB1 (seemingly) agreed port C unlock (may) be needed for COMP0(C0-/C1-) input assigned GPIO pins C4,C7.

    I'd love to see that (long past) "agreement - I'm in doubt.   Much doubt!

    It is only Port pins C0-C3 which are now (and have been) so encumbered!

    Good luck.

  • Agree it seems that would be the case C0-C3.

    Bottom of page last post I do suggest the CR register protects lower bits leaving the upper nibble unprotected safe to write. One post above that CB1 corrected to use (|=) but if the lower nibble is locked who cares. Suppose the confusion stems from past PMT added unlock CR prior to configuring C4, C7. Seemed like good idea at the time.

    e2e.ti.com/.../335848

    Good suggestion CB1 (|=) left a lasting impression. Had TI actually confirmed the CR of TM4C1294NCPX0 was working as stated. Year ago post was RA1 silicon & PMT 1.0.4 and presently RA2 datasheet Rev 14.