Hi all, I have two questions.
Is there a way to prevent ETPWM output to stop at emulation halt ?
Is it possible to control polarity of ETPWM pin output when ETPWM clock (VCLK4) is halted?
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Hi all, I have two questions.
Is there a way to prevent ETPWM output to stop at emulation halt ?
Is it possible to control polarity of ETPWM pin output when ETPWM clock (VCLK4) is halted?
Hello Anthony and Sunil,
thank you, all is clear now.
So i can change FREE_SOFT to get etpwm clock running during emulation halt and using TZSEL / TZCTL i can define the behavior of etpwm pins at emulation event .