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Hi,
I have a doubt regarding the priority scheme in the TMS570LC4357. I have worked with Cortex M series processors, so I'm aware of the fact that those processors have a register PRIMASK which allows the processor to control disable interrupts below a certain priority. I am trying to find an equivalent mechanism for this processor i.e Cortex R5F. I did find a certain register VICSWPRIORITYMASK which is a part of PL192 ARM Primecell Vectored Interrupt Controller(refer to the image below. Snapshot taken from the ARM website). I hope the TMS570LC4357 is using a modified version of this particular VIC for interrupt handling. Could you please verify if I'm thinking about this correctly. This particular Mask register provides a 16 bit priority masking, I am also finding it difficult to understand how the VIM inside the TMS570 is mapping priorities to CHAPMAP. Since there are 128 different channels each associated with a different priority. However this module says there are 16 priorities levels only.
