What is the root cause for missing the second byte with the DMA and SPI (non-MibSPI) and GCLK to HCLK ratio of 3:1?
Will the second byte always be missed with a GCLK to HCLK ratio of 3:1?
I would prefer to work around the issue without changing the clocks. I will put my project at significant risk by changing the clock settings (affecting all the peripherals) which have been used and tested for over a year.
The original problem for the TMS570LC4357 was posted here:
