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SPI : Using SSI1 on tm4c123gh6pz

sg_34
Intellectual 500 points
Other Parts Discussed in Thread: MSP430F247, TM4C123GH6PZ

Hi,

I'm using TM4C123GH6PZ to exchange datas with MSP430F247 trough SPI.

My code is working when using SSI0, but not when using SSI1, and I don't understand what happen.

Could you help if you have an idea? Here is my source code (Chip Select isn't used):

void spi_init(void){
        
    //Enable SSI module    
    SysCtlPeripheralEnable(CC_SSI_SYSCTL_PERIPH);
        
    //Configure mux pins
    GPIOPinConfigure(CC_SSICLK_PIN);
    GPIOPinConfigure(CC_SSIRX_PIN);
    GPIOPinConfigure(CC_SSITX_PIN);

    //Select the SSI function for these pins
    GPIOPinTypeSSI(CC_GPIO_PORT_BASE, CC_SSI_CLK | CC_SSI_TX | CC_SSI_RX );

    //Configure SSI port parameters
    SSIConfigSetExpClk(CC_SSI_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_1, SSI_MODE_MASTER, 40000, 8);

    //Enable SSI  
    SSIEnable(CC_SSI_BASE);
}

When using SSI0 :

    #define CC_SSI_SYSCTL_PERIPH        SYSCTL_PERIPH_SSI0
    #define CC_SSI_BASE                               SSI0_BASE    
    #define CC_GPIO_PORT_BASE              GPIO_PORTA_BASE        
    #define CC_SSI_CLK                                 GPIO_PIN_2
    #define CC_SSI_TX                                    GPIO_PIN_4
    #define CC_SSI_RX                                    GPIO_PIN_5    
    #define CC_SSICLK_PIN                          GPIO_PA2_SSI0CLK    
    #define CC_SSIRX_PIN                             GPIO_PA4_SSI0RX    
    #define CC_SSITX_PIN                             GPIO_PA5_SSI0TX            

When using SSI1:

    #define CC_SSI_SYSCTL_PERIPH        SYSCTL_PERIPH_SSI1
    #define CC_SSI_BASE                              SSI1_BASE    
    #define CC_GPIO_PORT_BASE             GPIO_PORTF_BASE        
    #define CC_SSI_CLK                                GPIO_PIN_2
    #define CC_SSI_TX                                    GPIO_PIN_1
    #define CC_SSI_RX                                   GPIO_PIN_0   
    #define CC_SSICLK_PIN                          GPIO_PF2_SSI1CLK    
    #define CC_SSIRX_PIN                            GPIO_PF1_SSI1RX    
    #define CC_SSITX_PIN                             GPIO_PF0_SSI1TX            

  • 0
    Guru 26105 points

    Hi,

    Port F pin 0 is also NMI pin, which must be re-configured to GPIO prior any other use. See other responses related to PF0.

  • 0 in reply to Petrei
    Intellectual 500 points
    Ok, if I understand, I need to add these two lines
    HWREG(GPIO_PORTF_BASE+GPIO_O_LOCK) = GPIO_LOCK_KEY; //Unlock
    HWREG(GPIO_PORTF_BASE+GPIO_O_CR) |= 0X01; // Enable PF0 AFS
    HWREG(GPIO_PORTF_BASE+GPIO_O_LOCK) =0; // Relock

    My init function became :
    void spi_init(void){

    //Enable SSI module
    SysCtlPeripheralEnable(CC_SSI_SYSCTL_PERIPH);

    // Unlock PF0 (NMI) to be able to use SSI1
    HWREG(GPIO_PORTF_BASE+GPIO_O_LOCK) = GPIO_LOCK_KEY; //Unlock
    HWREG(GPIO_PORTF_BASE+GPIO_O_CR) |= 0X01; // Enable PF0 AFS
    HWREG(GPIO_PORTF_BASE+GPIO_O_LOCK) =0; // Relock

    //Configure mux pins
    GPIOPinConfigure(CC_SSICLK_PIN);
    GPIOPinConfigure(CC_SSIRX_PIN);
    GPIOPinConfigure(CC_SSITX_PIN);

    //Select the SSI function for these pins
    GPIOPinTypeSSI(CC_GPIO_PORT_BASE, CC_SSI_CLK | CC_SSI_TX | CC_SSI_RX );

    //Configure SSI port parameters
    SSIConfigSetExpClk(CC_SSI_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_1, SSI_MODE_MASTER, 40000, 8);

    //Enable SSI
    SSIEnable(CC_SSI_BASE);
    }

    Is it OK?

    Board isn't available at this time, I'll test tomorrow

    Thanks