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TM4C1294NCPDT GPIO PE3 as digital input interfering with ADC

Sergio Kamakura
Expert 2495 points
Other Parts Discussed in Thread: TM4C1294NCPDT

Hi

We found a serious bug in GPIO PE3 pin of TM4C1294NCPDT chip.

We are using PE3 as digital input in our custom board. We use PK0 and PE5 as analog input ( AIN16 and AIN8 respectively ).

When PE3 receives 1 as input, occur a drift in ADC conversion of aproximately 20% up.

After a long headache, searching for noises, instabilities, crosstalks between printed-circuit tracks, we began to suspect on the chip.

We found in page 11 of spmz850d.pdf errata, the following information:

ADC#13 A Glitch can Occur on pin PE3 When Using any ADC Analog Input Channel to
Sample


Revision(s) Affected: 1, 2, and 3.
Description A glitch may occur on PE3 when using any ADC analog input channel (AINx) to sample.
This glitch can occur when PE3 is configured as an analog input channel (AINx) and
happens at the end of the ADC conversion. These glitches will not affect analog
measurements on PE3 when configured as AIN0 as long as the specified source
resistance is met.
Workaround(s) A 1kΩ external pull-up or pull-down on PE3 will help to minimize the magnitude of the
glitch to 200 mV or less.

But, the problem is not restricted to PE3 as analog input, but  digital input as well, as we painfully found.

Is there a fix to this issue?

Thanks,

Sergio

  • 0
    TI__Guru**** 244400 points
    Hello Sergio,

    Is the PE3 a driven input or does it have a Pull Up on the pin such that it is driven 0 and pull up to logic 1?

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Expert 2495 points
    Hi Amit

    PE3 is connected to a 74LVC244 output, without any pull-up, and is programmed as GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU:

    GPIOPinTypeGPIOInput(GPIO_PORTE_BASE, GPIO_PIN_3 );
    GPIOPadConfigSet(GPIO_PORTE_BASE, GPIO_PIN_3 , GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);

    Thanks,

    Sergio
  • 0 in reply to Sergio Kamakura
    TI__Guru**** 244400 points
    Hello Sergio,

    The internal Pull Up is a very weak pull up of 16Kohms as shown in the configuration lines. Does the issue occur when the line is driven to 1 or when the 74LVC244 tristates the line causing the Pull Up to come into affect?

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Expert 2495 points
    Hi Amit

    The problem occurs when PE3 is driven to 1. The 74LVC244 never tristates. I use other inputs in the same GPIO port and others doesn't cause any problem.

    Thanks,

    Sergio
  • 0 in reply to Sergio Kamakura
    TI__Guru**** 244400 points
    Hello Sergio.

    OK, so when the value is driven to 1 from 74LVC244 it causes a reading issue on the other channels. If that is the case can you try to put for example a dummy channel on the ADC sequencer before sampling other analog inputs? Does that yield better results?

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Expert 2495 points
    Hi Amit

    It is not my case, sorry.

    I have 2 analog inputs only, each driving an ADC alone, so I have PK0 associated to ADC0 and PE5 associated to ADC1.

    We are using sequence 3. The main problem is over ADC0, that must monitor AC line with precision of 1%, but, with the issue we are discussing, the drift on ADC0 is over 10% when PE3 receives digital level 1, that causes false alerts to the system.

    You don't have any previous complaint about this kind of issue?

    Perhaps, it is the case to switch to another pin. I asked to our hardware designer about this possibility and he said that it is not a problem. In fact, he is already making this modification ( prototyping ) to test if the problem is over with another pin. The candidate is PD2 pin.

    As soon we have the results about PD2, I will post to you.

    Thanks,

    Sergio
  • 0 in reply to Sergio Kamakura
    TI__Guru**** 244400 points
    Hello Sergio,

    What I am suggesting may not require any board modification. Instead of using SS3, use SS2 with two sequence steps. The first channel sampled is a spare channel with Pull Down enabled in the IO before the actual analog channel is sampled in the 2nd step of the sample sequencer. Thus incorrect voltage sampled in the S/H cap is discharged by the spare channel.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Expert 2495 points

    Hi Amit

    Good morning.

    We moved to PD2 and the issue is over.

    I think that, even placing a dummy analog input before sampling PK0 will not totally fix the problem, because, sequential sampling of PK0 show the same drift on ADC and, with your suggestion, this drift should decay through sequential samples ( while PE3 is in 1 ) and this is not occurring. Probably the internal leakage into S/H CAP is high enough to place some charge into S/H CAP between samplings and a significative error will be introduced into measurement. This is not acceptable.

    We decided to maintain PD2 in place of PE3.

    PE3 is out of game, forever.

    Anyway, thank you very much for your great support.

    Sergio

  • 0 in reply to Sergio Kamakura
    TI__Guru**** 244400 points
    Hello Sergio,

    Yes, the PE3 has a weak pull down which may not be sufficient to discharge the S/H cap,. My intent was to avoid any board change on your side.

    Regards
    Amit