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SPI TC4C123GH6PM query

Genius 3300 points
Other Parts Discussed in Thread: TM4C123GH6PM

I have written code for SPI, freescale mode. using driverlib 2.1.1.71 & keil 5.13.0.0.

1. I don't want to use SSI0Fss. Since I have two SPi slaves connected, so selecting two GPIo fro CS select purpose.
I didn't configure the Fss pin in code. is it enough to do so?


2. Page 965 of tm4c123gh6pm, says that pull-ups can be used on SPI to avoid any wrong state.
Do I should make pull-ups on all three pins clk, miso, mosi in any mode0-3
Or I should use pull-down in mode0 for clock?
Or I should use pull-ups only irrespective of mode.

Is below method correct to configure pull-ups
HWREG(GPIO_PORTA_AHB_BASE + GPIO_O_PUR) = HWREG(GPIO_PORTA_AHB_BASE + GPIO_O_PUR) | REG32_BIT_5;

3. In peripheral lib, SSIIntEnable() has four int flags: SSI_TXFF, SSI_RXFF, SSI_RXTO, or SSI_RXOR.
while SSIIntClear() has only two clear flags: SSI_RXTO , SSI_RXOR.
Does Tx flags automatically cleared by hardware?

4. How to diable fifo in SSI.
I want to transmit/receive only last byte written.

5. I have written code for SPI below in loopback mode & using AHB base for gpio pins.
I have checked on tm4c123gxl lauchpad & its working.
Is it ok ?

/* enable SSI0 module */    
    SysCtlPeripheralDisable(SYSCTL_PERIPH_SSI0);
    SysCtlPeripheralReset(SYSCTL_PERIPH_SSI0);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
    while( (!(SysCtlPeripheralReady(SYSCTL_PERIPH_SSI0)))  &&  (--ready_count));
    if(0U == ready_count)   /* if periph not ready take action */
    {
    }        
    
/* enable clk */
    SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOA);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
    while( (!(SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOA)))  &&  (--ready_count));
    if(0U == ready_count)   /* if periph not ready take action */
    {
    }      
    GPIOPinConfigure(GPIO_PA2_SSI0CLK);
    GPIOPinTypeSSI(GPIO_PORTA_AHB_BASE , GPIO_PIN_2);
    HWREG(GPIO_PORTA_AHB_BASE + GPIO_O_PUR) = HWREG(GPIO_PORTA_AHB_BASE + GPIO_O_PUR) | REG32_BIT_5;
    
/* enable rx */
    GPIOPinConfigure(GPIO_PA4_SSI0RX);
    GPIOPinTypeSSI(GPIO_PORTA_AHB_BASE , GPIO_PIN_4);    
    HWREG(GPIO_PORTA_AHB_BASE + GPIO_O_PUR) = HWREG(GPIO_PORTA_AHB_BASE + GPIO_O_PUR) | REG32_BIT_5;
    
/* enable tx */  
    GPIOPinConfigure(GPIO_PA5_SSI0TX);
    GPIOPinTypeSSI(GPIO_PORTA_AHB_BASE , GPIO_PIN_5);       
    HWREG(GPIO_PORTA_AHB_BASE + GPIO_O_PUR) = HWREG(GPIO_PORTA_AHB_BASE + GPIO_O_PUR) | REG32_BIT_5;
    
/* disable SPi first */ 
    SSIDisable(SSI0_BASE);
    SSIDMADisable(SSI0_BASE , SSI_DMA_RX | SSI_DMA_TX);
    SSIIntDisable(SSI0_BASE , SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR);
    SSIIntClear(SSI0_BASE , SSI_RXTO | SSI_RXOR);
    
/* SPI clock & congig */    
    SSIClockSourceSet(SSI0_BASE , SSI_CLOCK_SYSTEM);
    SSIConfigSetExpClk(SSI0_BASE , SysCtlClockGet() , SSI_FRF_MOTO_MODE_0 , SSI_MODE_MASTER , 1000000U , 8U);
    HWREG(SSI0_BASE + SSI_O_CR1) |= SSI_CR1_LBM;  /* enable loopback mode */
    SSIEnable(SSI0_BASE);
    
    uint8_t tx_byte = 0U;
    uint8_t rx_byte;
    uint32_t temp;
    while(1)
    {
        while(SSIBusy(SSI0_BASE));
        SSIDataPut(SSI0_BASE , (uint32_t)tx_byte);
        while(SSIBusy(SSI0_BASE));
        SSIDataGet(SSI0_BASE , &temp);
        rx_byte = (uint8_t)temp;
        if(rx_byte)
        {
        }
        tx_byte++;
        
    }    

  • Hello VT

    #1. Yes, you can do without configuring FSS pin.
    #2. The use of Pull Up depends on the state of the CLK in each of the mode's when in idle state.
    #3. Yes, those two flags for interrupt clear are handled by the data write or read.
    #4. The FIFO for SSI is always available and cannot be enabled or disabled
    #5. If the code works all of the time, then it should be OK.

    Regards
    Amit
  • Hi Amit,

    reagrding pullup-down on SSi pins:
    Three pins on SSi are there: MISO.MOSi & CLK. And four SSI modes 0-3.

    I think in all 4 modes, for MOSI & MISO : I can use pull-down always.
    While in CLK, when CLk polarity is high then pull-up. And when CLk polarity is low then pull-down.

    Is it right?
  • Vindhyachal Takniki said:
    While in CLK, when CLk polarity is high then pull-up. And when CLk polarity is low then pull-down.

    Cannot the exact opposite choice of pull-up/down be made - as your method "enables/encourages" the clocking of illegal data?   To my thinking - we want the MCU to actively clock in the data - not the (rather random) influence of a fixed pull-up/down resistor...   Having the pull-up/down devices operating "against" the desired signal edges prevents (or gravely reduces) such unwanted clocking of "bad" data (by a "mindless" pull-up/down...)

  • Hello VT,

    The CLK pin is driven by the master. So it depends on the manner is configured.

    Regards
    Amit